- Jul 27, 2021
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Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com
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- Feb 04, 2021
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Lokesh Vutla authored
Sync all J7200 related v5.11-rc6 Linux kernel dts into U-Boot. MCU R5F nodes are not yet added in Linux kernel yet but were added in U-Boot. In order to avoid regressions, r5f nodes are kept intact. These will be added in kernel in future. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
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Add support for UHS modes by adding the regulators to power cycle and voltage switch the card. Also add pinmuxes required for each node Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com>
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- Sep 15, 2020
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The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MAIN domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by:
Suman Anna <s-anna@ti.com>
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The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by:
Suman Anna <s-anna@ti.com>
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- Aug 11, 2020
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Enable CPSW2G port to support networking in U-Boot Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Add wkup_gpio0 node required for detecting whether board mux is set HyperFlash. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Add USB related DT entries to enable USB device mode. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Lokesh Vutla authored
Add the basic a72 dts for j7200. Following nodes were supported: - UART - MMC SD - I2C - TISCI communication Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Vishal Mahaveer <vishalm@ti.com> Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com>
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