1. 20 Jul, 2022 2 commits
  2. 19 Jul, 2022 1 commit
    • Tom Rini's avatar
      Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi · fc97ff26
      Tom Rini authored
      To quote Andre:
      
      One prominent feature is the restructering of the clock driver, which
      allows to end up with one actual driver for all variants, although we
      still only compile in support for one SoC.
      Also contained are some initial SPI fixes, which should fix some
      problems, and enable SPI flash support for the F1C100s SoC. Those
      patches revealed more problems, I will queue fixes later on, but for
      now it should at least still work.
      Apart from some smaller fixes (for instance for NAND operation), there
      is also preparation for the upcoming Allwinner D1 support, in form of
      the USB PHY driver. There are more driver support patches to come.
      
      The gitlab CI completed successfully, including the build test for all
      160 sunxi boards. I also boot tested on a few boards, but didn't have
      time for more elaborate tests this time.
      fc97ff26
  3. 18 Jul, 2022 31 commits
    • Samuel Holland's avatar
      phy: sun4i-usb: Add D1 variant · 25ba5be1
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      D1 has a register layout like A100 and H616, with the moved SIDDQ bit.
      Unlike H616 it does not have any dependencies between PHY instances.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      25ba5be1
    • André Przywara's avatar
      phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling · b33ee49a
      André Przywara authored
      
      
      As Icenowy pointed out, newer manuals (starting with H6) actually
      document the register block at offset 0x800 as "HCI controller and PHY
      interface", also describe the bits in our "PMU_UNK1" register.
      Let's put proper names to those "unknown" variables and symbols.
      
      While we are at it, generalise the existing code by allowing a bitmap
      of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
      different bit for the SIDDQ control.
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      b33ee49a
    • Samuel Holland's avatar
      phy: sun4i-usb: Drop use of arch-specific headers · 64331352
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      Since commit 089ffd0a
      
       ("phy: sun4i-usb: Use CLK and RESET support")
      neither of these headers is used. Dropping them allows the driver to be
      architecture-independent.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      64331352
    • Samuel Holland's avatar
      sunxi: Move INITIAL_USB_SCAN_DELAY to driver Kconfig · a35628ec
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      This option is used only by the phy-sun4i-usb driver, which does not
      inherently depend on the ARM architecture.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      a35628ec
    • Tom Rini's avatar
      Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi · 905e779b
      Tom Rini authored
      - add Macronix Octal flash (JaimeLiao)
      905e779b
    • Jae Hyun Yoo's avatar
      47ed8b22
    • JaimeLiao's avatar
      mtd: spi-nor-core: Add support for Macronix Octal flash · 4290ed78
      JaimeLiao authored
      Adding Macronix Octal flash for Octal DTR support.
      
      The octaflash series can be divided into the following types:
      
      MX25 series : Serial NOR Flash.
      MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
      LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
      LW/UW series : Support simultaneous Read-while-Write operation in multiple
                     bank architecture. Read-while-write feature which means read
                     data one bank while another bank is programing or erasing.
      
      MX25LM : 3.0V Octal I/O
       -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
      
      MX25UM : 1.8V Octal I/O
       -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7525/MX25UM51245G%20Extreme%20Speed,%201.8V,%20512Mb,%20v1.0.pdf
      
      MX66LM : 3.0V Octal I/O with stacked die
       -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7929/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
      
      MX66UM : 1.8V Octal I/O with stacked die
       -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
      
      
      
      MX25LW : 3.0V Octal I/O with Read-while-Write
      MX25UW : 1.8V Octal I/O with Read-while-Write
      MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
      MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
      
      About LW/UW series, please contact us freely if you have any
      questions. For adding Octal NOR Flash IDs, we have validated
      each Flash on plateform zynq-picozed.
      
      As below are the SFDP table dump.
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2943c
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx66uw2g345gx0
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345gx0
      zynq> hexdump mx66uw2g345gx0
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 001f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2853b
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx66lm1g45g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66lm1g45g
      zynq> hexdump mx66lm1g45g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 6987 0001 1282 e200 02cc 3867
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 6666
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
      0000130 3514 001c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2853a
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25lm51245g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm51245g
      zynq> hexdump mx25lm51245g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7989 0001 128d e200 02cc 4467
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 6666
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
      0000130 3514 001c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2863a
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25lw51245g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lw51245g
      zynq> hexdump mx25lw51245g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 0000 0000 0000 0000
      0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 6666
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
      0000130 3514 001c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28539
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25lm25645g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25lm25645g
      zynq> hexdump mx25lm25645g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 6666
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
      0000130 3514 001c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2843c
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx66uw2g345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw2g345g
      zynq> hexdump mx66uw2g345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 7fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7987 0001 1284 e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 001f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2803b
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx66um1g45g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66um1g45g
      zynq> hexdump mx66um1g45g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7989 0001 128d e200 02cc 4467
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 3514 809c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2813b
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx66uw1g45g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx66uw1g45g
      zynq> hexdump mx66uw1g45g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 3fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2813a
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw51245g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51245g
      zynq> hexdump mx25uw51245g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 7777
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0000 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c2843a
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw51345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw51345g
      zynq> hexdump mx25uw51345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 1fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f e200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28039
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25um25645g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25645g
      zynq> random: fast init done
      zynq> hexdump mx25um25645g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7987 0001 1284 d200 02cc 3867
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 3514 809c 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28139
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw25645g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25645g
      zynq> hexdump mx25uw25645g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7989 0001 128d d200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28339
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25um25345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25um25345g
      zynq> hexdump mx25um25345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 6987 0001 1282 d200 02cc 3867
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0904 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28439
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw25345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw25345g
      zynq> hexdump mx25uw25345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 0fff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7987 0001 1284 d200 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28138
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw12845g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12845g
      zynq> hexdump mx25uw12845g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 0000 0000 0000 0000
      0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f c900 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28438
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw12345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw12345g
      zynq> hexdump mx25uw12345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 07ff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f c900 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28137
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw6445g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6445g
      zynq> hexdump mx25uw6445g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 7989 0001 128d c400 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 a37c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id
      c28437
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer
      macronix
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/partname
      mx25uw6345g
      zynq> cat /sys/bus/spi/devices/spi0.0/spi-nor/sfdp > mx25uw6345g
      zynq> hexdump mx25uw6345g
      0000000 4653 5044 0108 fd04 0700 1401 0040 ff00
      0000010 0187 1c01 0090 ff00 000a 0801 0100 ff00
      0000020 0005 0501 0120 ff00 0084 0201 0134 ff00
      0000030 0000 0000 0000 0000 ffff ffff ffff ffff
      0000040 20e5 ff8a ffff 03ff ff00 ff00 ff00 ff00
      0000050 ffee ffff ffff ff00 ffff ff00 200c d810
      0000060 ff00 ff00 798b 0001 128f c400 04cc 4667
      0000070 b030 b030 bdf4 5cd5 0000 ff00 1010 2000
      0000080 0000 0000 0000 237c 0048 0000 0000 8888
      0000090 0000 0000 0000 4000 d10f f3ff d10f f3ff
      00000a0 0500 9000 0500 b100 2b00 9500 2b00 9600
      00000b0 7172 b803 7172 b803 0000 0000 a390 8218
      00000c0 c000 9669 0000 0000 0000 0000 7172 9800
      00000d0 7172 b800 7172 9900 0000 0000 7172 9800
      00000e0 7172 f800 7172 9900 7172 f900 0000 0000
      00000f0 0000 0000 1501 d001 7172 d806 0000 5086
      0000100 0000 0106 0000 0000 0002 0301 0200 0000
      0000110 0000 0106 0000 0000 0000 0672 0200 0000
      0000120 ee00 69c0 7272 7171 d800 f6f7 0a00 0000
      0000130 4514 8098 0643 000f dc21 ffff ffff ffff
      0000140 ffff ffff ffff ffff ffff ffff ffff ffff
      
      Signed-off-by: default avatarJaimeLiao <jaimeliao.tw@gmail.com>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      4290ed78
    • Jan Kiszka's avatar
      sf: Query write-protection status before operating the flash · f3a56dda
      Jan Kiszka authored
      
      
      Do not suggest successful operation if a flash area to be changed is
      actually locked, thus will not execute the request. Rather report an
      error and bail out. That's way more user-friendly than asking them to
      manually check for this case.
      
      Derived from original patch by Chao Zeng.
      
      Signed-off-by: Jan Kiszka's avatarJan Kiszka <jan.kiszka@siemens.com>
      Acked-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      f3a56dda
    • Jan Kiszka's avatar
      mtd: spi: Convert is_locked callback to is_unlocked · 513c6071
      Jan Kiszka authored
      There was no user of this callback after 5b66fdb2
      
       anymore, and its
      semantic as now inconsistent between stm and sst26. What we need for the
      upcoming new usecase is a "completely unlocked" semantic. So consolidate
      over this.
      
      Signed-off-by: Jan Kiszka's avatarJan Kiszka <jan.kiszka@siemens.com>
      Acked-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      513c6071
    • Vaishnav Achath's avatar
      spl: spl_spi: add spi_nor_remove() to soft reset flash · cd2f9031
      Vaishnav Achath authored
      
      
      On probe, the SPI NOR core will put a flash in 8D mode if it
      supports it. But Linux as of now expects to get the flash in
      1S mode. Handing the flash to Linux in Octal DTR mode means
      the kernel will fail to detect the flash.
      
      This commit adds an option to soft reset the flash after
      spl_spi_load_image() so that the flash can be reset to 1S mode
      and subsequent spi-nor probe in Linux does not fail, since
      spl_spi_load_image() performs spi_flash_probe() the remove is
      added after completion loading images in spi_flash_probe() itself.
      
      Tested on J721E EVM with 5.10 Linux kernel.
      
      Linux spi-nor probe without the fix:
      root@j7-evm:~# dmesg | grep spi-nor
      [    4.928023] spi-nor spi0.0: unrecognized JEDEC id bytes: ff ff ff ff ff ff
      [    4.934938] spi-nor: probe of spi0.0 failed with error -2
      
      Linux spi-nor probe with the fix:
      root@j7-evm:~# dmesg | grep spi-nor
      [    4.904484] spi-nor spi0.0: mt35xu512aba (65536 Kbytes)
      
      Signed-off-by: default avatarVaishnav Achath <vaishnav.a@ti.com>
      Acked-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      cd2f9031
    • JaimeLiao's avatar
      mtd: spi-nor: Parse SFDP SCCR Map · bebdc237
      JaimeLiao authored
      
      
      Parse SCCR 22nd dword and check DTR Octal Mode Enable
      Volatile bit for Octal DTR enable
      
      Signed-off-by: default avatarJaimeLiao <jaimeliao.tw@gmail.com>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      bebdc237
    • JaimeLiao's avatar
      mtd: spi-nor-core: Adding different type of command extension in Soft Reset · 68ad73b7
      JaimeLiao authored
      
      
      Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
      in the begging of probe.
      
      Command extension type is not standardized across flash vendors in DTR mode.
      
      For suiting different vendor flash devices, adding a flag to seperate types for
      soft reset on boot.
      
      Signed-off-by: default avatarJaimeLiao <jaimeliao.tw@gmail.com>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      68ad73b7
    • JaimeLiao's avatar
      mtd: spi-nor: add support for Macronix Octal flash · df3d5f9e
      JaimeLiao authored
      Follow patch <f6adec1a> (Allow using Micron mt35xu512aba
      in Octal DTR mode).
      Enable Octal DTR mode with 20 dummy cycles to allow running at the
      maximum supported frequency for adding Macronix flash in Octal DTR mode.
       -https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
      
      
      
      Signed-off-by: default avatarJaimeLiao <jaimeliao.tw@gmail.com>
      Reviewed-by: Jagan Teki's avatarJagan Teki <jagan@amarulasolutions.com>
      df3d5f9e
    • Markus Hoffrogge's avatar
      sunxi-nand: fix the PIO instead of DMA implementation · 5fd30ed7
      Markus Hoffrogge authored and André Przywara's avatar André Przywara committed
      The sunxi nand SPL loader was broken at least for SUN4I,
      SUN5I and SUN7I SOCs since the implementation change
      from DMA to PIO usage - commit 6ddbb1e9
      
      .
      
      Root cause for this issue is the NFC control flag NFC_CTL_RAM_METHOD
      being set by method nand_apply_config.
      
      This flag controls the bus being used for the NFCs internal RAM access.
      It must be set for the DMA use case only.
      See A33_Nand_Flash_Controller_Specification.pdf page 12.
      
      This fix is tested by myself on a Cubietruck A20 board.
      Others should test it on new generation SOCs as well.
      
      Signed-off-by: default avatarMarkus Hoffrogge <mhoffrogge@gmail.com>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      5fd30ed7
    • Michal Suchanek's avatar
      configs: sunxi: OrangePi Zero: enable Macronix flash support · 4a9f37df
      Michal Suchanek authored and André Przywara's avatar André Przywara committed
      The boards that come with a flash memory pre-soldered have a Macronix
      flash chip.
      
      Fixes: 280294c5
      
       ("sunxi: boards: Enable SPI flash support in U-Boot proper")
      Signed-off-by: default avatarMichal Suchanek <msuchanek@suse.de>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      4a9f37df
    • Michal Suchanek's avatar
      sunxi: lcd: Move range from kconfig description to definition. · e038c7a2
      Michal Suchanek authored and André Przywara's avatar André Przywara committed
      
      
      KConfig has range option, use it instead of notice in the option
      descrition.
      
      Signed-off-by: default avatarMichal Suchanek <msuchanek@suse.de>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      e038c7a2
    • André Przywara's avatar
      sunxi: licheepi_nano: enable SPI flash · 642e6574
      André Przywara authored
      
      
      Many LicheePi Nano boards come with SPI flash soldered, which already
      works for booting the SPL and loading U-Boot proper.
      With the updated DTB, we can now also use the SPI flash from U-Boot
      proper, so enable the bits in the defconfig, to allow loading binaries
      from SPI flash.
      There seem to be board revisions with a Winbond SPI chip, but also
      others with an XTX chip, so include support for both: the actual chip
      used will be autodetected.
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      642e6574
    • André Przywara's avatar
      spi: sunxi: Add support for F1C100s SPI controller · 8649995c
      André Przywara authored
      
      
      The SPI controllers in the Allwinner F1Cx00 series of SoCs are
      compatible to the H3 IP. The only difference in the integration is
      the missing mod clock in the F1C100, instead the SPI clock is directly
      derived from the AHB clock.
      We *should* be able to model this through the DT, but the addition of
      get_rate() requires quite some refactoring, so it's not really worth in
      this simple case: We programmed both the PLL_PERIPH to 600 MHz and the
      PLL/AHB divider to 3 in the SPL, so we know the SPI base clock is 200
      MHz. Since we used a hard coded fixed clock rate of 24 MHz for all the
      other SoCs so far, we can as well do the same for the F1C100.
      
      Define the SPI input clock and maximum frequency differently when
      compiling for the F1C100 SoC.
      Also adjust the power-of-2 divider programming, because that uses a
      "minus one" encoding, compared to the other SoCs.
      
      This allows to enable SPI flash support for the F1C100 boards.
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      8649995c
    • André Przywara's avatar
      spi: sunxi: improve SPI clock calculation · fcd6d936
      André Przywara authored
      
      
      The current SPI clock divider calculation has two problems:
      - We use a normal round-down division, which results in a divider
        typically being too small, resulting in a too high frequency on the bus.
      - The calculaction for the power-of-two divider is very inaccurate, and
        again rounds down, which might lead to wild bus frequencies.
      
      This wasn't a real problem so far, since most chips can handle slightly
      higher bus frequencies just fine. Also the actual speed was mostly lost
      anyway, due to release_bus() reseting the device. And the power-of-2
      calculation was probably never used, because it only applies to
      frequencies below 47 KHz.
      However this will become a problem for the F1C100s support, due to its
      much higher base frequency.
      
      Calculate a safe divider correctly (using round-up), and re-use that
      value when calculating the power-of-2 value. We also separate the
      maximum frequency and the input clock on the way, since they will be
      different for the F1C100s.
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      fcd6d936
    • André Przywara's avatar
      spi: sunxi: refactor SPI speed/mode programming · 239dfd11
      André Przywara authored
      As George rightfully pointed out [1], the spi-sunxi driver programs the
      speed and mode settings only when the respective functions are called,
      but this gets lost over a call to release_bus(). That asserts the
      reset line, thus forces each SPI register back to its default value.
      Adding to that, trying to program SPI_CCR and SPI_TCR might be pointless
      in the first place, when the reset line is still asserted (before
      claim_bus()), so those setting won't apply most of the time. In reality
      I see two nested claim_bus() calls for the first use, so settings between
      the two would work (for instance for the initial "sf probe"). However
      later on the speed setting is not programmed into the hardware anymore.
      
      So far we get away with that default frequency, because that is a rather
      tame 24 MHz, which most SPI flash chips can handle just fine.
      
      Move the actual register programming into a separate function, and use
      .set_speed and .set_mode just to set the variables in our priv structure.
      Then we only call this new function in claim_bus(), when we are sure
      that register accesses actually work and are preserved.
      
      [1] https://lore.kernel.org/u-boot/20210725231636.879913-17-me@yifangu.com/
      
      
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Reported-by: default avatarGeorge Hilliard <thirtythreeforty@gmail.com>
      239dfd11
    • Icenowy Zheng's avatar
      spi: sunxi: use XCH status to detect in-progress transfer · 56e497eb
      Icenowy Zheng authored and André Przywara's avatar André Przywara committed
      
      
      The current detection of RX FIFO depth seems to be not reliable, and
      XCH will self-clear when a transfer is done.
      
      Check XCH bit when polling for transfer finish.
      
      Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      56e497eb
    • Samuel Holland's avatar
      net: sun8i-emac: Drop use of arch-specific header · 68655e6c
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      This header is not used since commit abdbefba
      
       ("net: sun8i_emac: Use
      consistent clock bitfield definitions"). Dropping it allows the driver
      to be architecture-independent.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      68655e6c
    • Samuel Holland's avatar
      net: sun8i-emac: Downgrade printf during probe to debug · 62ee0433
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      This just prints the PHY mode taken from the devicetree. It does not
      need to be printed during every boot, and also avoids an unwanted
      line break for the "net: " reporting line.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      62ee0433
    • André Przywara's avatar
      sunxi: configs: streamline include/configs/sun*.h wrappers · 93118438
      André Przywara authored
      
      
      For mostly historic reasons we had configuration headers for each
      Allwinner CPU "family". These days they are mostly just including one
      common header, with the rest being somewhat empty.
      There were attempts to remove them, and to just use the one common header
      to begin with, but this has implications to the build system, which me
      might not be ready for, yet.
      
      To document this behaviour, and to avoid something sneaking in over
      time, make those files all the same (minus the CPU family name and
      the copyrights), and add a comment explaining that.
      This makes it easier to just remove those files later on, when needed
      and possible.
      
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Reviewed-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      93118438
    • Samuel Holland's avatar
      reset: sunxi: Reuse the platform data from the clock driver · 66391263
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      The clock and reset drivers use the exact same platform data. Simplify
      them by sharing the object. This is safe because the parent device
      (the clock device) always gets its driver model callbacks run first.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Acked-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      66391263
    • Samuel Holland's avatar
      reset: sunxi: Convert driver private data to platform data · 3fb1988a
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      The reason here is the same as the reason for changing the clock driver:
      platform data can be provided when binding the driver.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      3fb1988a
    • Samuel Holland's avatar
      clk: sunxi: Convert driver private data to platform data · 5af97b6f
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      All of the driver private data should really be platform data since it
      is determined statically (selected by the compatible string or extracted
      from the devicetree). Move everything to platform data, so it can be
      provided when binding the driver. This is useful for SPL, or for
      instantiating the driver as part of an MFD.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      5af97b6f
    • Samuel Holland's avatar
      clk: sunxi: Use a single driver for all variants · 46fa23f9
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      Now that all of the variants use the same bind/probe functions and ops,
      there is no need to have a separate driver for each variant. Since most
      SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
      of firmware size and RAM.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      [Andre: add F1C100s support]
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      46fa23f9
    • Samuel Holland's avatar
      reset: sunxi: Get the reset count from the CCU descriptor · d39088ad
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      This allows all of the clock drivers to use a common bind function.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      [Andre: add F1C100s support]
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      d39088ad
    • Samuel Holland's avatar
      clk: sunxi: Prevent out-of-bounds gate array access · 6827aba3
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      Because the gate arrays are not given explicit sizes, the arrays are
      only as large as the highest-numbered gate described in the driver.
      However, only a subset of the CCU clocks are needed by U-Boot. So there
      are valid clock specifiers with indexes greater than the size of the
      arrays. Referencing any of these clocks causes out-of-bounds access.
      Fix this by checking the identifier against the size of the array.
      
      Fixes: 0d47bc70
      
       ("clk: Add Allwinner A64 CLK driver")
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      6827aba3
    • Samuel Holland's avatar
      clk: sunxi: Store the array sizes in the CCU descriptor · 49b2b0a2
      Samuel Holland authored and André Przywara's avatar André Przywara committed
      
      
      The reset array size is currently used for bounds checking in the reset
      driver. The same bounds check should really be done in the clock driver.
      
      Currently, the array size is provided to the reset driver separately
      from the CCU descriptor, which is a bit strange. Let's do this the usual
      way, with the array sizes next to the arrays themselves.
      
      Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
      Reviewed-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      [Andre: add F1C100s support]
      Signed-off-by: André Przywara's avatarAndre Przywara <andre.przywara@arm.com>
      49b2b0a2
  4. 14 Jul, 2022 6 commits
    • Tom Rini's avatar
      Merge branch '2022-07-14-migrate-wiki-to-sphinx' · 26f6f7fb
      Tom Rini authored
      - Merge the majority of the relevant wiki content to doc/process/ and
        convert to Sphinx.  Begin cleaning up and modernizing the content as
        well to match current process.  There is still more work to be done in
        this regard.
      26f6f7fb
    • Tom Rini's avatar
      doc: Add in the historical release statistics found on the wiki · 9bf08a63
      Tom Rini authored
      
      
      The wiki had gitdm-generated release statistics starting with v1.3.0.
      Re-generate this information as Sphinx.  This aims to be as historically
      accurate as possible and so some company renames were kept to their old
      rather than current name until we had made the switch previously.
      
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      9bf08a63
    • Tom Rini's avatar
      doc: process: Correct and expand slightly on the Merge Window concept · 105bccb3
      Tom Rini authored
      
      
      For quite a long time we've been using a 3 week, rather than 2 week,
      merge window as it was only 2 weeks during the timeframe where we did 2
      month rather than 3 month releases.  This corrects the places that still
      had 2 weeks and tries to make things a bit clearer overall.
      
      Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      105bccb3
    • Tom Rini's avatar
      doc: Add doc/develop/release_cycle.rst · 6b484ba6
      Tom Rini authored
      
      
      Migrate the RelaseCycle wiki page to Sphinx.  In terms of visible
      changes, we stop having a dynamic countdown to when the release is.  And
      we drop the year-based statistics, that were not being kept up to date.
      For the moment, we only link to statistics for v2022.07 but will add
      back the historical data in a subsequent patch.
      
      Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      6b484ba6
    • Tom Rini's avatar
      process.rst: Modernize the "Workflow of a Custodian" section · 61550734
      Tom Rini authored
      
      
      The "Workflow of a Custodian" section on the wiki had not been changed
      in quite some time to reflect how the process has been functioning for
      some time.  First, update some links to point to modern and current
      sources of information.
      
      Second, and more overarching, reword much of the section.  This expands
      on the expectations of both custodians and developers when it comes to
      rebasing patches.  Rework the final points to be clearer that Custodians
      are expected to do their best to test the changes and ask for help when
      needed, as well as that pull requests are expected in a timely manner.
      
      Cc: Claudius Heine <ch@denx.de>
      Cc: Martin Bonner <martingreybeard@gmail.com>
      Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      61550734
    • Tom Rini's avatar
      process.rst: Perform minor cleanups · 50a7adca
      Tom Rini authored
      
      
      - Use gender-neutral language to refer to the user, consistently.
      - Reword a few places so that they read more naturally.
      - Make the long standing practice around "Twilight Time" more clear,
        hopefully.
      - Replace a reference to MAKEALL with a reference to CI testing as
        that's the current requirement.
      
      Cc: Claudius Heine <ch@denx.de>
      Cc: Martin Bonner <martingreybeard@gmail.com>
      Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      50a7adca