board: asus: grouper: dynamically detect correct SPL configuration

Use PMIC detection mechanism to find correct configuration.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

board/asus/grouper/Makefile

@@ -6,9 +6,6 @@
 #  (C) Copyright 2021
 #  Svyatoslav Ryhel <clamor95@gmail.com>
 
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DM_PMIC_MAX77663) += grouper-spl-max.o
-obj-$(CONFIG_DM_PMIC_TPS65910) += grouper-spl-ti.o
-endif
+obj-$(CONFIG_SPL_BUILD) += grouper-spl.o
 
 obj-y += grouper.o

board/asus/grouper/grouper-spl-ti.c

-// SPDX-License-Identifier: GPL-2.0+
-/*
- *  T30 Grouper TI SPL stage configuration
- *
- *  (C) Copyright 2010-2013
- *  NVIDIA Corporation <www.nvidia.com>
- *
- *  (C) Copyright 2022
- *  Svyatoslav Ryhel <clamor95@gmail.com>
- */
-
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/tegra_i2c.h>
-#include <linux/delay.h>
-
-#define TPS65911_I2C_ADDR		(0x2D << 1)
-#define TPS65911_VDDCTRL_OP_REG		0x28
-#define TPS65911_VDDCTRL_SR_REG		0x27
-#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
-#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
-
-#define TPS62361B_I2C_ADDR		(0x60 << 1)
-#define TPS62361B_SET3_REG		0x03
-#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
-
-void pmic_enable_cpu_vdd(void)
-{
-	/* Set VDD_CORE to 1.200V. */
-	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
-
-	udelay(1000);
-
-	/*
-	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-	 * First set VDD to 1.0125V, then enable the VDD regulator.
-	 */
-	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
-	udelay(1000);
-	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
-	udelay(10 * 1000);
-}

board/asus/grouper/grouper-spl-max.c → board/asus/grouper/grouper-spl.c

 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  T30 Grouper MAX SPL stage configuration
+ *  T30 Grouper SPL stage configuration
  *
  *  (C) Copyright 2010-2013
  *  NVIDIA Corporation <www.nvidia.com>
@@ -9,8 +9,11 @@
  *  Svyatoslav Ryhel <clamor95@gmail.com>
  */
 
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/tegra_i2c.h>
+#include <spl_gpio.h>
 #include <linux/delay.h>
 
 #define MAX77663_I2C_ADDR		(0x3C << 1)
@@ -25,7 +28,39 @@
 #define MAX77663_REG_GPIO4		0x3A
 #define MAX77663_REG_GPIO4_DATA		(0x0100 | MAX77663_REG_GPIO4)
 
-void pmic_enable_cpu_vdd(void)
+#define TPS65911_I2C_ADDR		(0x2D << 1)
+
+#define TPS65911_VDDCTRL_OP_REG		0x28
+#define TPS65911_VDDCTRL_SR_REG		0x27
+#define TPS65911_VDDCTRL_OP_DATA	(0x2400 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA	(0x0100 | TPS65911_VDDCTRL_SR_REG)
+
+#define TPS62361B_I2C_ADDR		(0x60 << 1)
+
+#define TPS62361B_SET3_REG		0x03
+#define TPS62361B_SET3_DATA		(0x4600 | TPS62361B_SET3_REG)
+
+/*
+ *	PCB_ID[8] is GMI_CS2_N_PK3
+ *
+ *	    PMIC module detection
+ *	==============================
+ *	PCB_ID[8]	0	1
+ *	PMIC		Maxim	TI
+ */
+static bool ti_pmic_detected(void)
+{
+	/* Configure pinmux */
+	pinmux_set_func(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_FUNC_GMI);
+	pinmux_set_pullupdown(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PULL_DOWN);
+	pinmux_tristate_enable(PMUX_PINGRP_GMI_CS2_N_PK3);
+	pinmux_set_io(PMUX_PINGRP_GMI_CS2_N_PK3, PMUX_PIN_INPUT);
+
+	spl_gpio_input(NULL, TEGRA_GPIO(K, 3));
+	return spl_gpio_get_value(NULL, TEGRA_GPIO(K, 3));
+}
+
+static void max_enable_cpu_vdd(void)
 {
 	/* Set VDD_CORE to 1.200V. */
 	tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_SD1_DATA);
@@ -43,3 +78,28 @@ void pmic_enable_cpu_vdd(void)
 	/* Set 32k-out gpio state */
 	tegra_i2c_ll_write(MAX77663_I2C_ADDR, MAX77663_REG_GPIO4_DATA);
 }
+
+static void ti_enable_cpu_vdd(void)
+{
+	/* Set VDD_CORE to 1.200V. */
+	tegra_i2c_ll_write(TPS62361B_I2C_ADDR, TPS62361B_SET3_DATA);
+
+	udelay(1000);
+
+	/*
+	 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+	 * First set VDD to 1.0125V, then enable the VDD regulator.
+	 */
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_OP_DATA);
+	udelay(1000);
+	tegra_i2c_ll_write(TPS65911_I2C_ADDR, TPS65911_VDDCTRL_SR_DATA);
+	udelay(10 * 1000);
+}
+
+void pmic_enable_cpu_vdd(void)
+{
+	if (ti_pmic_detected())
+		ti_enable_cpu_vdd();
+	else
+		max_enable_cpu_vdd();
+}