1. 22 Sep, 2021 3 commits
  2. 21 Sep, 2021 1 commit
  3. 20 Sep, 2021 2 commits
  4. 19 Sep, 2021 1 commit
  5. 18 Sep, 2021 3 commits
  6. 17 Sep, 2021 11 commits
    • Tom Rini's avatar
      Merge branch '2021-09-17-TI-platform-updates' · d0b8c9a2
      Tom Rini authored
      - Assorted bugfixes for TI platforms
      d0b8c9a2
    • Nishanth Menon's avatar
      arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup · ee91d465
      Nishanth Menon authored
      
      
      With Device Manager firmware in an elf file form, we cannot load the FIT
      image to the exact same address as any of the executable sections of the
      elf file itself is located.
      
      However, the device tree descriptions for the ARMV8 bootloader/OS
      includes DDR regions only the final sections in DDR where the Device
      Manager firmware is actually executing out of.
      
      As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
      by starting the Armv8 ahead of parsing the elf and copying the correct
      sections to the required memories creates a race condition where the
      ARMv8 could overwrite the elf image loaded from the FIT image prior to
      the R5 completing parsing and putting the correct sections of elf in
      the required memory locations. OR create rather obscure debug conditions
      where data in the section is being modified by ARMV8 OS while the elf
      copy is in progress.
      
      To prevent all these conditions, lets make sure that the elf parse and
      copy operations are completed ahead of ARMv8 being released to execute.
      
      We will pay a penalty of elf copy time, but that is a valid tradeoff in
      comparison to debug of alternate scenarios.
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      ee91d465
    • Roger Quadros's avatar
      arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge · 6887f8e0
      Roger Quadros authored
      
      
      NB0 is bridge to SRAM and NB1 is bridge to DDR.
      
      To ensure that SRAM transfers are not stalled due to delays during DDR
      refreshes, SRAM traffic should be higher priority (threadmap=2) than
      DDR traffic (threadmap=0).
      
      This fixup is critical to provide deterministic access latency to
      MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
      to incorrect reset values (has no erratum id) and statically setting
      things up should be done independent of usecases and board.
      
      This specific style of Northbridge configuration is specific only to
      AM65x devices, follow-on K3 devices have different data prioritization
      schemes (ASEL and the like) and hence the fixup applies purely to
      AM65x.
      
      Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
      case of SR1 devices, on SR2 devices, lockups were not observed so far
      but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
      throughput.
      Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
      Acked-by: default avatarAndrew F. Davis <afd@ti.com>
      Acked-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
      Acked-by: default avatarBenoit Parrot <bparrot@ti.com>
      [Jan: rebased, dropped used define, extended commit log]
      Signed-off-by: Jan Kiszka's avatarJan Kiszka <jan.kiszka@siemens.com>
      [Nishanth: Provide relevant context in the commit message]
      Signed-off-by: Nishanth Menon<nm@ti.com>
      6887f8e0
    • Suman Anna's avatar
      clk: ti: k3: Update driver to account for divider flags · cfd50dfb
      Suman Anna authored
      
      
      The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
      turn serve as inputs to other HSDIV output clocks. These clocks use
      the actual value to compute the divider clock rate, and need to be
      registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
      driver and data lacks the infrastructure to pass in divider flags.
      Update the driver and data to account for these divider flags.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      cfd50dfb
    • Dave Gerlach's avatar
      clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write · d3c56e2a
      Dave Gerlach authored
      There are three different divider values in the DIV_CTRL register
      controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
      function writes the entire register when programming plld, even though
      plld only resides in the lower 6 bits.
      
      Change the plld programming to read-modify-write to only affect the
      relevant bits for plld and to preserve the other two divider values
      present in the upper 16 bits, otherwise they will always get set to zero
      when programming plld.
      
      Fixes: 0aa2930c
      
       ("clk: add support for TI K3 SoC PLL")
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      d3c56e2a
    • Dave Gerlach's avatar
      arm: mach-k3: Add note to auto-generated files · ae8d3d23
      Dave Gerlach authored
      
      
      Add a note to the automatically generated clk-data and dev-data files
      for j721e and j7200 to indicate that they are in fact auto-generated and
      should not be hand edited.
      
      Also adjust TI URL to use https instead of http and also add an empty
      line before first header inclusion.
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      ae8d3d23
    • Suman Anna's avatar
      arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks · 326c03b5
      Suman Anna authored
      The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
      divisors to generate the final FOUTPOSTDIV clock. These are in sequence
      with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
      has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
      opposite of the actual implementation. Fix the data by simply adjusting
      the register bit-shifts.
      
      The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
      register values, fix these as well.
      
      Fixes: 277729ea
      
       ("arm: mach-k3: Add platform data for j721e and j7200")
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      326c03b5
    • Suman Anna's avatar
      arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks · f1a815d0
      Suman Anna authored
      The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
      divisors to generate the final FOUTPOSTDIV clock. These are in sequence
      with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
      has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
      opposite of the actual implementation. Fix the data by simply adjusting
      the register bit-shifts.
      
      The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
      register values, fix these as well.
      
      Fixes: 277729ea
      
       ("arm: mach-k3: Add platform data for j721e and j7200")
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      f1a815d0
    • Suman Anna's avatar
      arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub · d86a089d
      Suman Anna authored
      
      
      Add a weak release_resources_for_core_shutdown() stub implementation
      that can be overridden by actual implementation if a SoC supports that
      function.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Reviewed-by: default avatarNishanth Menon <nm@ti.com>
      d86a089d
    • Suman Anna's avatar
      firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h · 04662755
      Suman Anna authored
      
      
      The common TI SCI header file uses some macros from err.h and these
      get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
      the linux/err.h header file in this header file directly rather
      than relying on source files to include it to eliminate any
      potential build errors.
      
      While at this, reorder the existing header file include to the
      beginning of the file.
      Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
      Reviewed-by: default avatarNishanth Menon <nm@ti.com>
      04662755
    • Christophe Leroy's avatar
      MAINTAINERS: POWERPC MPC8XX: Update email address · 12ff1a8d
      Christophe Leroy authored
      
      
      Our email addresses have changed from @c-s.fr to @csgroup.eu
      
      Update entry in MAINTAINERS
      Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
      12ff1a8d
  7. 15 Sep, 2021 5 commits
  8. 14 Sep, 2021 9 commits
    • Tom Rini's avatar
      Prepare v2021.10-rc4 · bb92678c
      Tom Rini authored
      
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      bb92678c
    • Tom Rini's avatar
      configs: Resync with savedefconfig · e3e2c643
      Tom Rini authored
      
      
      Rsync all defconfig files using moveconfig.py
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      e3e2c643
    • Alexandru Gagniuc's avatar
      image: Avoid erroneous double byte-swap in CRC value · 1ac7580a
      Alexandru Gagniuc authored
      The hash algorithm selection was streamlined in commit 92055e13
      ("image: Drop if/elseif hash selection in calculate_hash()"). Said
      commit kept the call to cpu_to_uimage() to convert the CRC to big
      endian format.
      
      This would have been correct when calling crc32_wd(). However, the
      ->hash_func_ws member of crc32 points to crc32_wd_buf(), which already
      converts the CRC to big endian. On a little endian host, doing both
      conversions results in a little-endian CRC. This is incorrect.
      
      To remedy this, simply drop the call to cpu_to_uimage(), thus only
      doing the byte-order conversion once.
      
      Fixes: 92055e13
      
       ("image: Drop if/elseif hash selection in
             calculate_hash()")
      Tested-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      Signed-off-by: default avatarAlexandru Gagniuc <mr.nuke.me@gmail.com>
      1ac7580a
    • Tom Rini's avatar
      Merge branch '2021-09-14-assorted-fixes' · c6eac912
      Tom Rini authored
      - Assorted bugfixes
      c6eac912
    • Alexandru Gagniuc's avatar
      image: rsa: Move padding_algos to linker lists · de41f0ee
      Alexandru Gagniuc authored
      We are not guaranteed to have the padding_pkcs_15_verify symbol since
      commit 92c960bc ("lib: rsa: Remove #ifdefs from rsa.h"), and
      commit 61416fe9 ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY")
      
      The padding_algos only make sense with RSA verification, which can now
      be disabled in lieu of ECDSA. In fact this will lead to build failures
      because of the missing symbol mentioned earlier.
      
      To resolve this, move the padding_algos to a linker list, with
      declarations moved to rsa_verify.c. This is consistent with commit
      6909edb4
      
       ("image: rsa: Move verification algorithm to a linker list")
      
      One could argue that the added #ifdef USE_HOSTCC is ugly, and should
      be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would
      be inconsistent with the "cryptos" list. This logic for was not
      previously explored:
      
      Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is
      similar to something being declared. However, should #ifndef
      USE_HOSTCC be part of the macro, it would not be obvious that it
      behaves differently on host code and target code. Having the #ifndef
      outside the macro makes this obvious.
      
      Also, the #ifdef is not always necessary. For example ecda-verify
      makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs.
      The fundamental issue is a lack of separation of host and target code
      in rsa_verify. Therefore, the declaration of a padding algo with the
      external #ifdef is more readable and consistent.
      Signed-off-by: default avatarAlexandru Gagniuc <mr.nuke.me@gmail.com>
      de41f0ee
    • Yuan Fang's avatar
      pinctrl: fix typo · 423e324d
      Yuan Fang authored
      
      
      fix typo in pinctrl Kconfig file to avoid git commit failure on
      some commit hooks check.
      Signed-off-by: default avatarYuan Fang <fangyuanseu@gmail.com>
      423e324d
    • Oleksandr Suvorov's avatar
      lib: fix typos in Kconfig · 5145bc73
      Oleksandr Suvorov authored
      There are trivial typos in the Kconfig file. Fixed them.
      Also, fixed grammar in the descriptions with typos.
      
      Fixes: d56b4b19 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS")
      Fixes: 7264f292
      
       ("spl: fit: Eanble GZIP support for image decompression")
      Signed-off-by: default avatarOleksandr Suvorov <oleksandr.suvorov@foundries.io>
      Reviewed-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
      5145bc73
    • Heinrich Schuchardt's avatar
      lib/rsa: don't use NULL as key_id · d607dfd8
      Heinrich Schuchardt authored
      If keydir is not provided but name is we want to use name as key_id.
      
      But with the current coding name is only used on its own if it is NULL
      and keydir is provided which never occurs.
      
      Fixes: 824ee745
      
       ("lib/rsa: Use the 'keyfile' argument from mkimage")
      Signed-off-by: Heinrich Schuchardt's avatarHeinrich Schuchardt <xypron.glpk@gmx.de>
      Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      d607dfd8
    • Tom Rini's avatar
      Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi · 5c257573
      Tom Rini authored
      - a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
      5c257573
  9. 13 Sep, 2021 5 commits