nand_base.c 111 KB
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/*
 *  Overview:
 *   This is the generic MTD driver for NAND flash devices. It should be
 *   capable of working with almost all NAND chips currently available.
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 *
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 *	Additional technical information is available on
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 *	http://www.linux-mtd.infradead.org/doc/nand.html
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 *
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 *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
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 *		  2002-2006 Thomas Gleixner (tglx@linutronix.de)
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 *
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 *  Credits:
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 *	David Woodhouse for adding multichip support
 *
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 *	Aleph One Ltd. and Toby Churchill Ltd. for supporting the
 *	rework for 2K page size chips
 *
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 *  TODO:
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 *	Enable cached programming for 2k page size chips
 *	Check, if mtd->ecctype should be set to MTD_ECC_HW
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 *	if we have HW ECC support.
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 *	BBT table is not serialized, has to be fixed
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <common.h>
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#if CONFIG_IS_ENABLED(OF_CONTROL)
#include <fdtdec.h>
#endif
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#include <malloc.h>
#include <watchdog.h>
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#include <linux/err.h>
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#include <linux/compat.h>
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#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/nand_bch.h>
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#ifdef CONFIG_MTD_PARTITIONS
#include <linux/mtd/partitions.h>
#endif
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#include <asm/io.h>
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#include <linux/errno.h>
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/* Define default oob placement schemes for large and small page devices */
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static struct nand_ecclayout nand_oob_8 = {
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	.eccbytes = 3,
	.eccpos = {0, 1, 2},
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	.oobfree = {
		{.offset = 3,
		 .length = 2},
		{.offset = 6,
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		 .length = 2} }
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};

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static struct nand_ecclayout nand_oob_16 = {
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	.eccbytes = 6,
	.eccpos = {0, 1, 2, 3, 6, 7},
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	.oobfree = {
		{.offset = 8,
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		 . length = 8} }
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};

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static struct nand_ecclayout nand_oob_64 = {
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	.eccbytes = 24,
	.eccpos = {
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		   40, 41, 42, 43, 44, 45, 46, 47,
		   48, 49, 50, 51, 52, 53, 54, 55,
		   56, 57, 58, 59, 60, 61, 62, 63},
	.oobfree = {
		{.offset = 2,
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		 .length = 38} }
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};

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static struct nand_ecclayout nand_oob_128 = {
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	.eccbytes = 48,
	.eccpos = {
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		   80, 81, 82, 83, 84, 85, 86, 87,
		   88, 89, 90, 91, 92, 93, 94, 95,
		   96, 97, 98, 99, 100, 101, 102, 103,
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		   104, 105, 106, 107, 108, 109, 110, 111,
		   112, 113, 114, 115, 116, 117, 118, 119,
		   120, 121, 122, 123, 124, 125, 126, 127},
	.oobfree = {
		{.offset = 2,
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		 .length = 78} }
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};

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static int nand_get_device(struct mtd_info *mtd, int new_state);
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static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
			     struct mtd_oob_ops *ops);

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/*
 * For devices which display every fart in the system on a separate LED. Is
 * compiled away when LED support is disabled.
 */
DEFINE_LED_TRIGGER(nand_led_trigger);
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static int check_offs_len(struct mtd_info *mtd,
					loff_t ofs, uint64_t len)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	int ret = 0;

	/* Start address must align on block boundary */
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	if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
		pr_debug("%s: unaligned address\n", __func__);
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		ret = -EINVAL;
	}

	/* Length must align on block boundary */
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	if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
		pr_debug("%s: length not block aligned\n", __func__);
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		ret = -EINVAL;
	}

	return ret;
}

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/**
 * nand_release_device - [GENERIC] release chip
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 * @mtd: MTD device structure
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 *
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 * Release chip lock and wake up anyone waiting on the device.
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 */
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static void nand_release_device(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	/* De-select the NAND device */
	chip->select_chip(mtd, -1);
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}
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/**
 * nand_read_byte - [DEFAULT] read one byte from the chip
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 * @mtd: MTD device structure
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 *
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 * Default read function for 8bit buswidth
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 */
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uint8_t nand_read_byte(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return readb(chip->IO_ADDR_R);
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}

/**
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 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 * @mtd: MTD device structure
 *
 * Default read function for 16bit buswidth with endianness conversion.
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 *
 */
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static uint8_t nand_read_byte16(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
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}

/**
 * nand_read_word - [DEFAULT] read one word from the chip
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 * @mtd: MTD device structure
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 *
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 * Default read function for 16bit buswidth without endianness conversion.
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 */
static u16 nand_read_word(struct mtd_info *mtd)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	return readw(chip->IO_ADDR_R);
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}

/**
 * nand_select_chip - [DEFAULT] control CE line
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 * @mtd: MTD device structure
 * @chipnr: chipnumber to select, -1 for deselect
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 *
 * Default select function for 1 chip devices.
 */
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static void nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	switch (chipnr) {
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	case -1:
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		chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
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		break;
	case 0:
		break;

	default:
		BUG();
	}
}

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/**
 * nand_write_byte - [DEFAULT] write single byte to chip
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0]
 */
static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	chip->write_buf(mtd, &byte, 1);
}

/**
 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
 * @mtd: MTD device structure
 * @byte: value to write
 *
 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
 */
static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	uint16_t word = byte;

	/*
	 * It's not entirely clear what should happen to I/O[15:8] when writing
	 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
	 *
	 *    When the host supports a 16-bit bus width, only data is
	 *    transferred at the 16-bit width. All address and command line
	 *    transfers shall use only the lower 8-bits of the data bus. During
	 *    command transfers, the host may place any value on the upper
	 *    8-bits of the data bus. During address transfers, the host shall
	 *    set the upper 8-bits of the data bus to 00h.
	 *
	 * One user of the write_byte callback is nand_onfi_set_features. The
	 * four parameters are specified to be written to I/O[7:0], but this is
	 * neither an address nor a command transfer. Let's assume a 0 on the
	 * upper I/O lines is OK.
	 */
	chip->write_buf(mtd, (uint8_t *)&word, 2);
}

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#if !defined(CONFIG_BLACKFIN)
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static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
{
	int i;

	for (i = 0; i < len; i++)
		writeb(buf[i], addr);
}
static void ioread8_rep(void *addr, uint8_t *buf, int len)
{
	int i;

	for (i = 0; i < len; i++)
		buf[i] = readb(addr);
}

static void ioread16_rep(void *addr, void *buf, int len)
{
	int i;
 	u16 *p = (u16 *) buf;
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	for (i = 0; i < len; i++)
		p[i] = readw(addr);
}

static void iowrite16_rep(void *addr, void *buf, int len)
{
	int i;
        u16 *p = (u16 *) buf;

        for (i = 0; i < len; i++)
                writew(p[i], addr);
}
#endif

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/**
 * nand_write_buf - [DEFAULT] write buffer to chip
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 * @mtd: MTD device structure
 * @buf: data buffer
 * @len: number of bytes to write
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 *
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 * Default write function for 8bit buswidth.
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 */
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void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	iowrite8_rep(chip->IO_ADDR_W, buf, len);
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}

/**
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 * nand_read_buf - [DEFAULT] read chip data into buffer
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 * @mtd: MTD device structure
 * @buf: buffer to store date
 * @len: number of bytes to read
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 *
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 * Default read function for 8bit buswidth.
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 */
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void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	ioread8_rep(chip->IO_ADDR_R, buf, len);
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}

/**
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 * nand_write_buf16 - [DEFAULT] write buffer to chip
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 * @mtd: MTD device structure
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 * @buf: data buffer
 * @len: number of bytes to write
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 *
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 * Default write function for 16bit buswidth.
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 */
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void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 *p = (u16 *) buf;

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	iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
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}

/**
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 * nand_read_buf16 - [DEFAULT] read chip data into buffer
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 * @mtd: MTD device structure
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 * @buf: buffer to store date
 * @len: number of bytes to read
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 *
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 * Default read function for 16bit buswidth.
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 */
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void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 *p = (u16 *) buf;

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	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
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}

/**
 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
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 * @mtd: MTD device structure
 * @ofs: offset from device start
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 *
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 * Check, if the block is bad.
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 */
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static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
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{
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	int page, res = 0, i = 0;
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u16 bad;

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	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
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		ofs += mtd->erasesize - mtd->writesize;

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	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
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	do {
		if (chip->options & NAND_BUSWIDTH_16) {
			chip->cmdfunc(mtd, NAND_CMD_READOOB,
					chip->badblockpos & 0xFE, page);
			bad = cpu_to_le16(chip->read_word(mtd));
			if (chip->badblockpos & 0x1)
				bad >>= 8;
			else
				bad &= 0xFF;
		} else {
			chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
					page);
			bad = chip->read_byte(mtd);
		}
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		if (likely(chip->badblockbits == 8))
			res = bad != 0xFF;
		else
			res = hweight8(bad) < chip->badblockbits;
		ofs += mtd->writesize;
		page = (int)(ofs >> chip->page_shift) & chip->pagemask;
		i++;
	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
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	return res;
}

/**
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 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
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 * @mtd: MTD device structure
 * @ofs: offset from device start
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 *
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 * This is the default implementation, which can be overridden by a hardware
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 * specific driver. It provides the details for writing a bad block marker to a
 * block.
 */
static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	struct mtd_oob_ops ops;
	uint8_t buf[2] = { 0, 0 };
	int ret = 0, res, i = 0;

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	memset(&ops, 0, sizeof(ops));
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	ops.oobbuf = buf;
	ops.ooboffs = chip->badblockpos;
	if (chip->options & NAND_BUSWIDTH_16) {
		ops.ooboffs &= ~0x01;
		ops.len = ops.ooblen = 2;
	} else {
		ops.len = ops.ooblen = 1;
	}
	ops.mode = MTD_OPS_PLACE_OOB;

	/* Write to first/last page(s) if necessary */
	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
		ofs += mtd->erasesize - mtd->writesize;
	do {
		res = nand_do_write_oob(mtd, ofs, &ops);
		if (!ret)
			ret = res;

		i++;
		ofs += mtd->writesize;
	} while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);

	return ret;
}

/**
 * nand_block_markbad_lowlevel - mark a block bad
 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
 * This function performs the generic NAND bad block marking steps (i.e., bad
 * block table(s) and/or marker(s)). We only allow the hardware driver to
 * specify how to write bad block markers to OOB (chip->block_markbad).
 *
 * We try operations in the following order:
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 *  (1) erase the affected block, to allow OOB marker to be written cleanly
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 *  (2) write bad block marker to OOB area of affected block (unless flag
 *      NAND_BBT_NO_OOB_BBM is present)
 *  (3) update the BBT
 * Note that we retain the first error encountered in (2) or (3), finish the
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 * procedures, and dump the error in the end.
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*/
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static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	int res, ret = 0;
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	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
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		struct erase_info einfo;

		/* Attempt erase before marking OOB */
		memset(&einfo, 0, sizeof(einfo));
		einfo.mtd = mtd;
		einfo.addr = ofs;
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		einfo.len = 1ULL << chip->phys_erase_shift;
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		nand_erase_nand(mtd, &einfo, 0);
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		/* Write bad block marker to OOB */
		nand_get_device(mtd, FL_WRITING);
		ret = chip->block_markbad(mtd, ofs);
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		nand_release_device(mtd);
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	}
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	/* Mark block bad in BBT */
	if (chip->bbt) {
		res = nand_markbad_bbt(mtd, ofs);
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		if (!ret)
			ret = res;
	}

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	if (!ret)
		mtd->ecc_stats.badblocks++;
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	return ret;
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}

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/**
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 * nand_check_wp - [GENERIC] check if the chip is write protected
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 * @mtd: MTD device structure
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 *
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 * Check, if the device is write protected. The function expects, that the
 * device is already selected.
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 */
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static int nand_check_wp(struct mtd_info *mtd)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	/* Broken xD cards report WP despite being writable */
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	if (chip->options & NAND_BROKEN_XD)
		return 0;

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	/* Check the WP bit */
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	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
	return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
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}
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/**
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 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
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 * @mtd: MTD device structure
 * @ofs: offset from device start
 *
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 * Check if the block is marked as reserved.
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 */
static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	if (!chip->bbt)
		return 0;
	/* Return info from the table */
	return nand_isreserved_bbt(mtd, ofs);
}

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/**
 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
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 * @mtd: MTD device structure
 * @ofs: offset from device start
 * @allowbbt: 1, if its allowed to access the bbt area
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 *
 * Check, if the block is bad. Either by reading the bad block table or
 * calling of the scan function.
 */
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static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
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{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	if (!(chip->options & NAND_SKIP_BBTSCAN) &&
	    !(chip->options & NAND_BBT_SCANNED)) {
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		chip->options |= NAND_BBT_SCANNED;
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		chip->scan_bbt(mtd);
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	}

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	if (!chip->bbt)
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		return chip->block_bad(mtd, ofs);
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	/* Return info from the table */
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	return nand_isbad_bbt(mtd, ofs, allowbbt);
}

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/**
 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 * @mtd: MTD device structure
 *
 * Wait for the ready pin after a command, and warn if a timeout occurs.
 */
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void nand_wait_ready(struct mtd_info *mtd)
{
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	struct nand_chip *chip = mtd_to_nand(mtd);
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	u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
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	u32 time_start;
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	time_start = get_timer(0);
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	/* Wait until command is processed or timeout occurs */
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	while (get_timer(time_start) < timeo) {
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		if (chip->dev_ready)
			if (chip->dev_ready(mtd))
				break;
	}
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	if (!chip->dev_ready(mtd))
		pr_warn("timeout while waiting for chip to become ready\n");
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}
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EXPORT_SYMBOL_GPL(nand_wait_ready);
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/**
 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
 * @mtd: MTD device structure
 * @timeo: Timeout in ms
 *
 * Wait for status ready (i.e. command done) or timeout.
 */
static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	u32 time_start;

	timeo = (CONFIG_SYS_HZ * timeo) / 1000;
	time_start = get_timer(0);
	while (get_timer(time_start) < timeo) {
		if ((chip->read_byte(mtd) & NAND_STATUS_READY))
			break;
		WATCHDOG_RESET();
	}
};

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/**
 * nand_command - [DEFAULT] Send command to NAND device
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 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
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 *
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 * Send command to NAND device. This function is used for small page devices
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 * (512 Bytes per page).
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 */
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static void nand_command(struct mtd_info *mtd, unsigned int command,
			 int column, int page_addr)
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{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
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	/* Write out the command to the device */
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	if (command == NAND_CMD_SEQIN) {
		int readcmd;

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		if (column >= mtd->writesize) {
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			/* OOB area */
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			column -= mtd->writesize;
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			readcmd = NAND_CMD_READOOB;
		} else if (column < 256) {
			/* First 256 bytes --> READ0 */
			readcmd = NAND_CMD_READ0;
		} else {
			column -= 256;
			readcmd = NAND_CMD_READ1;
		}
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		chip->cmd_ctrl(mtd, readcmd, ctrl);
		ctrl &= ~NAND_CTRL_CHANGE;
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	}
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	chip->cmd_ctrl(mtd, command, ctrl);
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	/* Address cycle, when necessary */
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	ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
	/* Serially input address */
	if (column != -1) {
		/* Adjust columns for 16 bit buswidth */
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		if (chip->options & NAND_BUSWIDTH_16 &&
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				!nand_opcode_8bits(command))
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			column >>= 1;
		chip->cmd_ctrl(mtd, column, ctrl);
		ctrl &= ~NAND_CTRL_CHANGE;
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	}
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	if (page_addr != -1) {
		chip->cmd_ctrl(mtd, page_addr, ctrl);
		ctrl &= ~NAND_CTRL_CHANGE;
		chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
		/* One more address cycle for devices > 32MiB */
		if (chip->chipsize > (32 << 20))
			chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
	}
	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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	/*
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	 * Program and erase have their own busy handlers status and sequential
	 * in needs no delay
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	 */
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	switch (command) {
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	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
	case NAND_CMD_STATUS:
		return;

	case NAND_CMD_RESET:
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		if (chip->dev_ready)
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			break;
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		udelay(chip->chip_delay);
		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
			       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd,
			       NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
		nand_wait_status_ready(mtd, 250);
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		return;

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		/* This applies to read commands */
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	default:
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		/*
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		 * If we don't have access to the busy pin, we apply the given
		 * command delay
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		 */
		if (!chip->dev_ready) {
			udelay(chip->chip_delay);
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			return;
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		}
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	}
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in
	 * any case on any machine.
	 */
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	ndelay(100);

	nand_wait_ready(mtd);
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}

/**
 * nand_command_lp - [DEFAULT] Send command to NAND large page device
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 * @mtd: MTD device structure
 * @command: the command to be sent
 * @column: the column address for this command, -1 if none
 * @page_addr: the page address for this command, -1 if none
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 *
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 * Send command to NAND device. This is the version for the new large page
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 * devices. We don't have the separate regions as we have in the small page
 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
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 */
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static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
			    int column, int page_addr)
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{
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	register struct nand_chip *chip = mtd_to_nand(mtd);
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	/* Emulate NAND_CMD_READOOB */
	if (command == NAND_CMD_READOOB) {
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		column += mtd->writesize;
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		command = NAND_CMD_READ0;
	}
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	/* Command latch cycle */
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	chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
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	if (column != -1 || page_addr != -1) {
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		int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
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		/* Serially input address */
		if (column != -1) {
			/* Adjust columns for 16 bit buswidth */
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			if (chip->options & NAND_BUSWIDTH_16 &&
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			chip->cmd_ctrl(mtd, column, ctrl);
			ctrl &= ~NAND_CTRL_CHANGE;
			chip->cmd_ctrl(mtd, column >> 8, ctrl);
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		}
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		if (page_addr != -1) {
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			chip->cmd_ctrl(mtd, page_addr, ctrl);
			chip->cmd_ctrl(mtd, page_addr >> 8,
				       NAND_NCE | NAND_ALE);
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			/* One more address cycle for devices > 128MiB */
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			if (chip->chipsize > (128 << 20))
				chip->cmd_ctrl(mtd, page_addr >> 16,
					       NAND_NCE | NAND_ALE);
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		}
	}
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	chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
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	/*
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	 * Program and erase have their own busy handlers status, sequential
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	 * in and status need no delay.
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	 */
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	switch (command) {
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	case NAND_CMD_CACHEDPROG:
	case NAND_CMD_PAGEPROG:
	case NAND_CMD_ERASE1:
	case NAND_CMD_ERASE2:
	case NAND_CMD_SEQIN:
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	case NAND_CMD_RNDIN:
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	case NAND_CMD_STATUS:
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		return;
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	case NAND_CMD_RESET:
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		if (chip->dev_ready)
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			break;
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		udelay(chip->chip_delay);
		chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);
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		/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
		nand_wait_status_ready(mtd, 250);
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		return;

	case NAND_CMD_RNDOUT:
		/* No ready / busy check necessary */
		chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);
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		return;

	case NAND_CMD_READ0:
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		chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
			       NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
		chip->cmd_ctrl(mtd, NAND_CMD_NONE,
			       NAND_NCE | NAND_CTRL_CHANGE);

		/* This applies to read commands */
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	default:
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		/*
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		 * If we don't have access to the busy pin, we apply the given
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		 * command delay.
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		 */
		if (!chip->dev_ready) {
			udelay(chip->chip_delay);
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			return;
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		}
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	}
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in
	 * any case on any machine.
	 */
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	ndelay(100);

	nand_wait_ready(mtd);
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}

/**
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 * panic_nand_get_device - [GENERIC] Get chip for selected access
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 * @chip: the nand chip descriptor
 * @mtd: MTD device structure
 * @new_state: the state which is requested
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 *
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 * Used when in panic, no locks are taken.
 */
static void panic_nand_get_device(struct nand_chip *chip,
		      struct mtd_info *mtd, int new_state)
{
	/* Hardware controller shared among independent devices */
	chip->controller->active = chip;
	chip->state = new_state;
}

/**
 * nand_get_device - [GENERIC] Get chip for selected access
 * @mtd: MTD device structure
 * @new_state: the state which is requested
 *
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 */
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static int
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nand_get_device(struct mtd_info *mtd, int new_state)
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{
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	chip->state = new_state;
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	return 0;
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}

/**
 * panic_nand_wait - [GENERIC] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
 * @timeo: timeout
 *
 * Wait for command done. This is a helper function for nand_wait used when
 * we are in interrupt context. May happen when in panic and trying to write
 * an oops through mtdoops.
 */
static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
			    unsigned long timeo)
{
	int i;
	for (i = 0; i < timeo; i++) {
		if (chip->dev_ready) {
			if (chip->dev_ready(mtd))
				break;
		} else {
			if (chip->read_byte(mtd) & NAND_STATUS_READY)
				break;
		}
		mdelay(1);
	}
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}
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/**
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 * nand_wait - [DEFAULT] wait until the command is done
 * @mtd: MTD device structure
 * @chip: NAND chip structure
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 *
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 * Wait for command done. This applies to erase and program only.
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 */
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static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
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{
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	int status;
	unsigned long timeo = 400;
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	led_trigger_event(nand_led_trigger, LED_FULL);
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	/*
	 * Apply this short delay always to ensure that we do wait tWB in any
	 * case on any machine.
	 */
	ndelay(100);
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	chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
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 	u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
 	u32 time_start;
 
 	time_start = get_timer(0);
 	while (get_timer(time_start) < timer) {
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		if (chip->dev_ready) {
			if (chip->dev_ready(mtd))
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				break;
		} else {
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			if (chip->read_byte(mtd) & NAND_STATUS_READY)
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				break;
		}
	}
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	led_trigger_event(nand_led_trigger, LED_OFF);

	status = (int)chip->read_byte(mtd);
	/* This can happen if in case of timeout or buggy dev_ready */
	WARN_ON(!(status & NAND_STATUS_READY));
	return status;
}

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#define BITS_PER_BYTE 8

/**
 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
 * @buf: buffer to test
 * @len: buffer length
 * @bitflips_threshold: maximum number of bitflips
 *
 * Check if a buffer contains only 0xff, which means the underlying region
 * has been erased and is ready to be programmed.
 * The bitflips_threshold specify the maximum number of bitflips before
 * considering the region is not erased.
 * Note: The logic of this function has been extracted from the memweight
 * implementation, except that nand_check_erased_buf function exit before
 * testing the whole buffer if the number of bitflips exceed the
 * bitflips_threshold value.
 *
 * Returns a positive number of bitflips less than or equal to
 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
 * threshold.
 */
static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
{
	const unsigned char *bitmap = buf;
	int bitflips = 0;
	int weight;

	for (; len && ((uintptr_t)bitmap) % sizeof(long);
	     len--, bitmap++) {
		weight = hweight8(*bitmap);
		bitflips += BITS_PER_BYTE - weight;
		if (unlikely(bitflips > bitflips_threshold))
			return -EBADMSG;
	}

	for (; len >= 4; len -= 4, bitmap += 4) {
		weight = hweight32(*((u32 *)bitmap));
		bitflips += 32 - weight;
		if (unlikely(bitflips > bitflips_threshold))
			return -EBADMSG;
	}

	for (; len > 0; len--, bitmap++) {
		weight = hweight8(*bitmap);
		bitflips += BITS_PER_BYTE - weight;
		if (unlikely(bitflips > bitflips_threshold))
			return -EBADMSG;
	}

	return bitflips;
}

/**
 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
 *				 0xff data
 * @data: data buffer to test
 * @datalen: data length
 * @ecc: ECC buffer
 * @ecclen: ECC length
 * @extraoob: extra OOB buffer
 * @extraooblen: extra OOB length
 * @bitflips_threshold: maximum number of bitflips
 *
 * Check if a data buffer and its associated ECC and OOB data contains only
 * 0xff pattern, which means the underlying region has been erased and is
 * ready to be programmed.
 * The bitflips_threshold specify the maximum number of bitflips before
 * considering the region as not erased.
 *
 * Note:
 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
 *    different from the NAND page size. When fixing bitflips, ECC engines will
 *    report the number of errors per chunk, and the NAND core infrastructure
 *    expect you to return the maximum number of bitflips for the whole page.
 *    This is why you should always use this function on a single chunk and
 *    not on the whole page. After checking each chunk you should update your
 *    max_bitflips value accordingly.
 * 2/ When checking for bitflips in erased pages you should not only check
 *    the payload data but also their associated ECC data, because a user might
 *    have programmed almost all bits to 1 but a few. In this case, we
 *    shouldn't consider the chunk as erased, and checking ECC bytes prevent
 *    this case.
 * 3/ The extraoob argument is optional, and should be used if some of your OOB
 *    data are protected by the ECC engine.
 *    It could also be used if you support subpages and want to attach some
 *    extra OOB data to an ECC chunk.
 *
 * Returns a positive number of bitflips less than or equal to
 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
 * threshold. In case of success, the passed buffers are filled with 0xff.
 */
int nand_check_erased_ecc_chunk(void *data, int datalen,
				void *ecc, int ecclen,
				void *extraoob, int extraooblen,
				int bitflips_threshold)
{
	int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;

	data_bitflips = nand_check_erased_buf(data, datalen,