board.c 8.05 KB
Newer Older
1
2
3
4
5
6
7
8
9
10
11
12
13
/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
14
#include <mmc.h>
Hans de Goede's avatar
Hans de Goede committed
15
#include <i2c.h>
16
17
18
19
20
21
22
23
#include <serial.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
#endif
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
24
#include <asm/arch/spl.h>
25
26
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
27
#include <asm/arch/tzpc.h>
28
#include <asm/arch/mmc.h>
29

30
31
#include <linux/compiler.h>

Simon Glass's avatar
Simon Glass committed
32
33
34
struct fel_stash {
	uint32_t sp;
	uint32_t lr;
35
36
37
38
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
Simon Glass's avatar
Simon Glass committed
39
40
41
42
};

struct fel_stash fel_stash __attribute__((section(".data")));

43
static int gpio_init(void)
44
{
45
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
46
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
47
48
49
50
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
51
#if defined(CONFIG_MACH_SUN8I)
52
53
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
54
#else
55
56
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
57
#endif
58
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
59
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
60
61
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
62
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
63
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
64
65
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
66
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
67
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
68
69
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
70
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
71
72
73
74
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
Jens Kuske's avatar
Jens Kuske committed
75
76
77
78
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
79
80
81
82
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
83
84
85
86
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
87
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
88
89
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
90
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
91
92
93
94
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
95
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
96
97
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
98
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
Hans de Goede's avatar
Hans de Goede committed
99
100
101
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
102
103
104
105

	return 0;
}

106
int spl_board_load_image(void)
Simon Glass's avatar
Simon Glass committed
107
108
109
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);
110
111

	return 0;
Simon Glass's avatar
Simon Glass committed
112
113
}

114
void s_init(void)
115
{
116
117
118
119
120
121
	/*
	 * Undocumented magic taken from boot0, without this DRAM
	 * access gets messed up (seems cache related).
	 * The boot0 sources describe this as: "config ema for cache sram"
	 */
#if defined CONFIG_MACH_SUN6I
122
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
123
124
125
126
127
128
129
130
131
132
133
134
#elif defined CONFIG_MACH_SUN8I_A23
	uint version;

	/* Unlock sram version info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	version = readl(SUNXI_SRAMC_BASE + 0x24);
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	if ((version & 0xffff0000) == 0x16500000)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	else /* 0x1661 ? */
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
135
#endif
136

137
138
139
#if defined CONFIG_MACH_SUN6I || \
    defined CONFIG_MACH_SUN7I || \
    defined CONFIG_MACH_SUN8I
140
141
142
143
144
145
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n");
#endif
146
147
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
148
149
	tzpc_init();
#endif
150
151
152
153
154

	clock_init();
	timer_init();
	gpio_init();
	i2c_init_board();
155
	eth_init_board();
156
}
157

158
#ifdef CONFIG_SPL_BUILD
159
160
DECLARE_GLOBAL_DATA_PTR;

161
162
163
164
165
/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
u32 spl_boot_device(void)
{
166
	__maybe_unused struct mmc *mmc0, *mmc1;
167
	/*
168
169
170
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
171
172
173
174
175
176
177
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
178
179
180
181
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
182
	 */
183
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
Simon Glass's avatar
Simon Glass committed
184
		return BOOT_DEVICE_BOARD;
185
186

	/* The BROM will try to boot from mmc0 first, so try that first. */
187
#ifdef CONFIG_MMC
188
189
190
191
	mmc_initialize(gd->bd);
	mmc0 = find_mmc_device(0);
	if (sunxi_mmc_has_egon_boot_signature(mmc0))
		return BOOT_DEVICE_MMC1;
192
#endif
193
194
195
196
197

	/* Fallback to booting NAND if enabled. */
	if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
		return BOOT_DEVICE_NAND;

198
#ifdef CONFIG_MMC
199
200
	if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
		mmc1 = find_mmc_device(1);
201
		if (sunxi_mmc_has_egon_boot_signature(mmc1))
202
203
			return BOOT_DEVICE_MMC2;
	}
204
#endif
205
206
207

	panic("Could not determine boot source\n");
	return -1;		/* Never reached */
208
209
210
211
212
213
214
215
216
217
}

/* No confirmation data available in SPL yet. Hardcode bootmode */
u32 spl_boot_mode(void)
{
	return MMCSD_MODE_RAW;
}

void board_init_f(ulong dummy)
{
218
	spl_init();
219
220
221
222
223
224
225
226
227
228
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

229
230
void reset_cpu(ulong addr)
{
231
#ifdef CONFIG_SUNXI_GEN_SUN4I
Hans de Goede's avatar
Hans de Goede committed
232
233
234
235
236
237
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
Hans de Goede's avatar
Hans de Goede committed
238
239
240
241
242

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
243
244
#endif
#ifdef CONFIG_SUNXI_GEN_SUN6I
245
246
247
248
249
250
251
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
252
	while (1) { }
253
#endif
254
255
256
257
258
259
260
261
262
}

#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif