Skip to content
  • Hans de Goede's avatar
    sunxi: mmc: Properly setup mod-clk and clock sampling phases · fc3a8325
    Hans de Goede authored
    
    
    The sunxi mmc controller has both an internal clock divider, as well as
    the divider in the mod0-clk for the mmc controller.
    
    The internal divider cannot be used, as it conflicts with the setting of
    clock sampling phases which is done in the mod0-clk, so it must be set to
    0 (divide by 1).
    
    For some reason while the kernel has had this correct from day one, the
    u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
    internal divider depending on the desired speed. This is something which
    we've inherited from the original Allwinner u-boot sources, but while this
    has been fixed in Allwinner's own u-boot code at least for the A23 and later
    upstream u-boot was still doing this wrong.
    
    This commit fixes this, thereby also fixing mmc support not working reliable
    on the A23 (which seems more sensitive to this) and possible also fixes some
    other sunxi mmc issues.
    
    Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
    Acked-by: default avatarIan Campbell <ijc@hellion.org.uk>
    fc3a8325