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U-Boot
U-Boot
Commits
0e8a8a31
Commit
0e8a8a31
authored
Jul 27, 2018
by
Tom Rini
Browse files
Merge
git://git.denx.de/u-boot-fsl-qoriq
parents
11e40928
86b840b7
Changes
54
Hide whitespace changes
Inline
Side-by-side
Makefile
View file @
0e8a8a31
...
...
@@ -1111,8 +1111,8 @@ u-boot.sha1: u-boot.bin
u-boot.dis
:
u-boot
$(OBJDUMP)
-d
$<
>
$@
if
def
CONFIG_
T
PL
SPL_PAYLOAD
:=
tpl/u-boot-with-tpl.bin
if
neq
($(
CONFIG_
S
PL
_PAYLOAD),)
SPL_PAYLOAD
:=
$
(
CONFIG_SPL_PAYLOAD:
"%"
=
%
)
else
SPL_PAYLOAD
:=
u-boot.bin
endif
...
...
arch/arm/cpu/armv8/fsl-layerscape/doc/README.falcon
View file @
0e8a8a31
...
...
@@ -129,6 +129,16 @@ Example:
The "loadables" is not optional. It tells SPL which images to load into memory.
Falcon mode with QSPI boot
--------------------------
To use falcon mode with QSPI boot, SPL needs to be enabled. Similar to SD or
NAND boot, a RAM version full feature U-Boot is needed. Unlike SD or NAND boot,
SPL with QSPI doesn't need to combine SPL image with RAM version image. Two
separated images are used, u-boot-spl.pbl and u-boot.img. The former is SPL
image with RCW and PBI commands to load the SPL payload into On-Chip RAM. The
latter is RAM version U-Boot in FIT format (or legacy format if FIT is not
used).
Other things to consider
-----------------------
Falcon boot skips a lot of initialization in U-Boot. If Linux expects the
...
...
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file @
0e8a8a31
...
...
@@ -6,8 +6,6 @@
#include
<common.h>
#include
<fsl_immap.h>
#include
<fsl_ifc.h>
#include
<ahci.h>
#include
<scsi.h>
#include
<asm/arch/fsl_serdes.h>
#include
<asm/arch/soc.h>
#include
<asm/io.h>
...
...
@@ -330,36 +328,6 @@ void fsl_lsch3_early_init_f(void)
#endif
}
#ifdef CONFIG_SCSI_AHCI_PLAT
int
sata_init
(
void
)
{
struct
ccsr_ahci
__iomem
*
ccsr_ahci
;
#ifdef CONFIG_SYS_SATA2
ccsr_ahci
=
(
void
*
)
CONFIG_SYS_SATA2
;
out_le32
(
&
ccsr_ahci
->
ppcfg
,
AHCI_PORT_PHY_1_CFG
);
out_le32
(
&
ccsr_ahci
->
pp2c
,
AHCI_PORT_PHY2_CFG
);
out_le32
(
&
ccsr_ahci
->
pp3c
,
AHCI_PORT_PHY3_CFG
);
out_le32
(
&
ccsr_ahci
->
ptc
,
AHCI_PORT_TRANS_CFG
);
out_le32
(
&
ccsr_ahci
->
axicc
,
AHCI_PORT_AXICC_CFG
);
#endif
#ifdef CONFIG_SYS_SATA1
ccsr_ahci
=
(
void
*
)
CONFIG_SYS_SATA1
;
out_le32
(
&
ccsr_ahci
->
ppcfg
,
AHCI_PORT_PHY_1_CFG
);
out_le32
(
&
ccsr_ahci
->
pp2c
,
AHCI_PORT_PHY2_CFG
);
out_le32
(
&
ccsr_ahci
->
pp3c
,
AHCI_PORT_PHY3_CFG
);
out_le32
(
&
ccsr_ahci
->
ptc
,
AHCI_PORT_TRANS_CFG
);
out_le32
(
&
ccsr_ahci
->
axicc
,
AHCI_PORT_AXICC_CFG
);
ahci_init
((
void
__iomem
*
)
CONFIG_SYS_SATA1
);
scsi_scan
(
false
);
#endif
return
0
;
}
#endif
/* Get VDD in the unit mV from voltage ID */
int
get_core_volt_from_fuse
(
void
)
{
...
...
@@ -400,25 +368,6 @@ int get_core_volt_from_fuse(void)
}
#elif defined(CONFIG_FSL_LSCH2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int
sata_init
(
void
)
{
struct
ccsr_ahci
__iomem
*
ccsr_ahci
=
(
void
*
)
CONFIG_SYS_SATA
;
/* Disable SATA ECC */
out_le32
((
void
*
)
CONFIG_SYS_DCSR_DCFG_ADDR
+
0x520
,
0x80000000
);
out_le32
(
&
ccsr_ahci
->
ppcfg
,
AHCI_PORT_PHY_1_CFG
);
out_le32
(
&
ccsr_ahci
->
pp2c
,
AHCI_PORT_PHY2_CFG
);
out_le32
(
&
ccsr_ahci
->
pp3c
,
AHCI_PORT_PHY3_CFG
);
out_le32
(
&
ccsr_ahci
->
ptc
,
AHCI_PORT_TRANS_CFG
);
out_le32
(
&
ccsr_ahci
->
axicc
,
AHCI_PORT_AXICC_CFG
);
ahci_init
((
void
__iomem
*
)
CONFIG_SYS_SATA
);
scsi_scan
(
false
);
return
0
;
}
#endif
static
void
erratum_a009929
(
void
)
{
...
...
@@ -719,9 +668,6 @@ int qspi_ahb_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int
board_late_init
(
void
)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init
();
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust
();
#endif
...
...
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View file @
0e8a8a31
...
...
@@ -11,6 +11,7 @@
#include
<fsl_csu.h>
#include
<asm/arch/fdt.h>
#include
<asm/arch/ppa.h>
#include
<asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -21,6 +22,9 @@ u32 spl_boot_device(void)
#endif
#ifdef CONFIG_SPL_NAND_SUPPORT
return
BOOT_DEVICE_NAND
;
#endif
#ifdef CONFIG_QSPI_BOOT
return
BOOT_DEVICE_NOR
;
#endif
return
0
;
}
...
...
@@ -52,6 +56,7 @@ void spl_board_init(void)
void
board_init_f
(
ulong
dummy
)
{
icache_enable
();
/* Clear global data */
memset
((
void
*
)
gd
,
0
,
sizeof
(
gd_t
));
board_early_init_f
();
...
...
@@ -101,6 +106,9 @@ void board_init_f(ulong dummy)
gd
->
arch
.
tlb_addr
=
(
gd
->
ram_top
-
gd
->
arch
.
tlb_size
)
&
~
(
0x10000
-
1
);
gd
->
arch
.
tlb_allocated
=
gd
->
arch
.
tlb_addr
;
#endif
/* CONFIG_SPL_FSL_LS_PPA */
#if defined(CONFIG_QSPI_AHB_INIT) && defined(CONFIG_QSPI_BOOT)
qspi_ahb_init
();
#endif
}
#ifdef CONFIG_SPL_OS_BOOT
...
...
arch/arm/dts/fsl-ls1012a-2g5rdb.dts
View file @
0e8a8a31
...
...
@@ -40,3 +40,7 @@
&
duart0
{
status
=
"okay"
;
};
&
sata
{
status
=
"okay"
;
};
arch/arm/dts/fsl-ls1012a-qds.dtsi
View file @
0e8a8a31
...
...
@@ -125,3 +125,7 @@
status
=
"okay"
;
phy_type
=
"ulpi"
;
};
&
sata
{
status
=
"okay"
;
};
arch/arm/dts/fsl-ls1012a-rdb.dtsi
View file @
0e8a8a31
...
...
@@ -34,3 +34,7 @@
&
duart0
{
status
=
"okay"
;
};
&
sata
{
status
=
"okay"
;
};
arch/arm/dts/fsl-ls1012a.dtsi
View file @
0e8a8a31
...
...
@@ -134,6 +134,14 @@
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
};
usb0: usb2@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
...
...
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View file @
0e8a8a31
...
...
@@ -85,39 +85,7 @@ struct cpu_type {
#define SVR_DEV(svr) ((svr) >> 8)
#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
/* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
#define AHCI_PORT_PHY2_CFG 0x28184d1f
#define AHCI_PORT_PHY3_CFG 0x0e081509
#define AHCI_PORT_TRANS_CFG 0x08000029
#define AHCI_PORT_AXICC_CFG 0x3fffffff
#ifndef __ASSEMBLY__
/* AHCI (sata) register map */
struct
ccsr_ahci
{
u32
res1
[
0xa4
/
4
];
/* 0x0 - 0xa4 */
u32
pcfg
;
/* port config */
u32
ppcfg
;
/* port phy1 config */
u32
pp2c
;
/* port phy2 config */
u32
pp3c
;
/* port phy3 config */
u32
pp4c
;
/* port phy4 config */
u32
pp5c
;
/* port phy5 config */
u32
axicc
;
/* AXI cache control */
u32
paxic
;
/* port AXI config */
u32
axipc
;
/* AXI PROT control */
u32
ptc
;
/* port Trans Config */
u32
pts
;
/* port Trans Status */
u32
plc
;
/* port link config */
u32
plc1
;
/* port link config1 */
u32
plc2
;
/* port link config2 */
u32
pls
;
/* port link status */
u32
pls1
;
/* port link status1 */
u32
pcmdc
;
/* port CMD config */
u32
ppcs
;
/* port phy control status */
u32
pberr
;
/* port 0/1 BIST error */
u32
cmds
;
/* port 0/1 CMD status error */
};
#ifdef CONFIG_FSL_LSCH3
void
fsl_lsch3_early_init_f
(
void
);
int
get_core_volt_from_fuse
(
void
);
...
...
@@ -130,6 +98,9 @@ int board_setup_core_volt(u32 vdd);
void
init_pfe_scfg_dcfg_regs
(
void
);
#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
int
qspi_ahb_init
(
void
);
#endif
void
cpu_name
(
char
*
name
);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
...
...
board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg
0 → 100644
View file @
0e8a8a31
#QSPI clk
0957015c 40100000
#Configure Scratch register
09570600 00000000
09570604 10000000
#Disable CCI barrier tranaction
09570178 0000e010
09180000 00000008
#USB PHY frequency sel
09570418 0000009e
0957041c 0000009e
09570420 0000009e
#Serdes SATA
09eb1300 80104e20
09eb08dc 00502880
#PEX gen3 link
09570158 00000300
89400890 01048000
89500890 01048000
89600890 01048000
#Alt base register
09570158 00001000
#flush PBI data
096100c0 000fffff
#Change endianness
09550000 000f400c
board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg
0 → 100644
View file @
0e8a8a31
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
0c150010 0e000000 00000000 00000000
11335559 40005012 40025000 c1000000
00000000 00000000 00000000 00238800
20124000 00003101 00000096 00000001
board/freescale/ls2080ardb/ls2080ardb.c
View file @
0e8a8a31
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2017 NXP Semiconductors
* Copyright 2015 Freescale Semiconductor
* Copyright 2017 NXP
*/
#include
<common.h>
#include
<malloc.h>
...
...
common/spl/Kconfig
View file @
0e8a8a31
...
...
@@ -553,6 +553,16 @@ config SYS_OS_BASE
endif # SPL_OS_BOOT
config SPL_PAYLOAD
string "SPL payload"
default "tpl/u-boot-with-tpl.bin" if TPL
default "u-boot.bin"
help
Payload for SPL boot. For backward compability, default to
u-boot.bin, i.e. RAW image without any header. In case of
TPL, tpl/u-boot-with-tpl.bin. For new boards, suggest to
use u-boot.img.
config SPL_PCI_SUPPORT
bool "Support PCI drivers"
help
...
...
configs/ls1012a2g5rdb_qspi_defconfig
View file @
0e8a8a31
...
...
@@ -29,11 +29,12 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
#
CONFIG_BLK
is not set
CONFIG_BLK
=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_SYS_NS16550=y
...
...
@@ -44,3 +45,7 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI=y
CONFIG_AHCI=y
configs/ls1012afrdm_qspi_defconfig
View file @
0e8a8a31
...
...
@@ -31,6 +31,7 @@ CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
...
...
configs/ls1012aqds_qspi_defconfig
View file @
0e8a8a31
...
...
@@ -34,11 +34,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
#
CONFIG_BLK
is not set
CONFIG_BLK
=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
...
...
@@ -56,3 +57,8 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View file @
0e8a8a31
...
...
@@ -31,11 +31,12 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
#
CONFIG_BLK
is not set
CONFIG_BLK
=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_PCI=y
...
...
@@ -53,3 +54,8 @@ CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y
configs/ls1012ardb_qspi_defconfig
View file @
0e8a8a31
...
...
@@ -30,11 +30,12 @@ CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
#
CONFIG_BLK
is not set
CONFIG_BLK
=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_FSL_PFE=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
...
...
@@ -51,3 +52,8 @@ CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_DM_SCSI=y
CONFIG_SATA_CEVA=y
CONFIG_SCSI_AHCI=y
CONFIG_SCSI=y
CONFIG_AHCI=y
configs/ls1043ardb_sdcard_defconfig
View file @
0e8a8a31
...
...
@@ -4,7 +4,6 @@ CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
...
...
configs/ls1046aqds_qspi_defconfig
View file @
0e8a8a31
...
...
@@ -30,6 +30,7 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
...
...
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