Commit 0fd3d911 authored by Simon Glass's avatar Simon Glass
Browse files

dm: Use access methods for dev/uclass private data



Most drivers use these access methods but a few do not. Update them.

In some cases the access is not permitted, so mark those with a FIXME tag
for the maintainer to check.
Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
Acked-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarPratyush Yadav <p.yadav@ti.com>
parent 12559f5b
......@@ -52,7 +52,11 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
continue;
}
#ifdef CONFIG_DM_ETH
priv = dev_get_priv(dev);
#else
priv = dev->priv;
#endif
if (priv->flags & TSEC_SGMII)
continue;
......
......@@ -9,6 +9,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/pmic.h>
......@@ -165,7 +166,7 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev)
}
uc_pdata->type = REGULATOR_TYPE_FIXED;
dev->priv = (void *)*p;
dev_set_priv(dev, (void *)*p);
return 0;
}
......
......@@ -16,6 +16,7 @@
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/lpss.h>
#include <dm/device-internal.h>
/* Low-power Subsystem (LPSS) clock register */
enum {
......@@ -105,7 +106,7 @@ static int apl_ns16550_of_to_plat(struct udevice *dev)
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
dev->plat = plat;
dev_set_plat(dev, plat);
#else
int ret;
......
......@@ -18,7 +18,7 @@ static int slimbootloader_serial_of_to_plat(struct udevice *dev)
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
struct ns16550_plat *plat = dev->plat;
struct ns16550_plat *plat = dev_get_plat(dev);
if (!gd->arch.hob_list)
panic("hob list not found!");
......
......@@ -44,8 +44,10 @@ int clk_register(struct clk *clk, const char *drv_name,
}
clk->enable_count = 0;
/* Store back pointer to clk from udevice */
clk->dev->uclass_priv = clk;
/* FIXME: This is not allowed...should be allocated by driver model */
dev_set_uclass_priv(clk->dev, clk);
return 0;
}
......
......@@ -6,6 +6,7 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <linux/clk-provider.h>
static ulong clk_fixed_rate_get_rate(struct clk *clk)
......@@ -32,7 +33,8 @@ static int clk_fixed_rate_of_to_plat(struct udevice *dev)
dev_read_u32_default(dev, "clock-frequency", 0);
#endif
/* Make fixed rate clock accessible from higher level struct clk */
dev->uclass_priv = clk;
/* FIXME: This is not allowed */
dev_set_uclass_priv(dev, clk);
clk->dev = dev;
clk->enable_count = 0;
......
......@@ -15,6 +15,7 @@
#include <asm/arch-rockchip/cru_px30.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/px30-cru.h>
#include <linux/bitops.h>
......@@ -1458,7 +1459,7 @@ static int px30_clk_bind(struct udevice *dev)
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct px30_cru,
glb_srst_snd);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3036.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <linux/delay.h>
......@@ -353,7 +354,7 @@ static int rk3036_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -15,6 +15,7 @@
#include <asm/arch-rockchip/cru_rk3128.h>
#include <asm/arch-rockchip/hardware.h>
#include <bitfield.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3128-cru.h>
#include <linux/delay.h>
......@@ -581,7 +582,7 @@ static int rk3128_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
return 0;
......
......@@ -593,7 +593,7 @@ static int rk3188_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3188_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk322x.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/bitops.h>
......@@ -510,7 +511,7 @@ static int rk322x_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -1018,7 +1018,7 @@ static int rk3288_clk_bind(struct udevice *dev)
cru_glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
cru_glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -15,6 +15,7 @@
#include <asm/arch/cru_rk3308.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3308-cru.h>
#include <linux/bitops.h>
......@@ -1045,7 +1046,7 @@ static int rk3308_clk_bind(struct udevice *dev)
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
glb_srst_snd);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
#include <linux/bitops.h>
......@@ -823,7 +824,7 @@ static int rk3328_clk_bind(struct udevice *dev)
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -19,6 +19,7 @@
#include <asm/arch-rockchip/cru_rk3368.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>
#include <linux/delay.h>
......@@ -621,7 +622,7 @@ static int rk3368_clk_bind(struct udevice *dev)
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rk3368_cru,
glb_srst_snd_val);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -18,6 +18,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3399-cru.h>
#include <linux/bitops.h>
......@@ -1425,7 +1426,7 @@ static int rk3399_clk_bind(struct udevice *dev)
glb_srst_fst_value);
priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
glb_srst_snd_value);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -16,6 +16,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rv1108.h>
#include <asm/arch-rockchip/hardware.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rv1108-cru.h>
#include <linux/delay.h>
......@@ -697,7 +698,7 @@ static int rv1108_clk_bind(struct udevice *dev)
glb_srst_fst_val);
priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
glb_srst_snd_val);
sys_child->priv = priv;
dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
......
......@@ -89,15 +89,15 @@ int device_unbind(struct udevice *dev)
return log_msg_ret("child unbind", ret);
if (dev->flags & DM_FLAG_ALLOC_PDATA) {
free(dev->plat);
dev->plat = NULL;
free(dev_get_plat(dev));
dev_set_plat(dev, NULL);
}
if (dev->flags & DM_FLAG_ALLOC_UCLASS_PDATA) {
free(dev->uclass_plat);
free(dev_get_uclass_plat(dev));
dev->uclass_plat = NULL;
}
if (dev->flags & DM_FLAG_ALLOC_PARENT_PDATA) {
free(dev->parent_plat);
free(dev_get_parent_plat(dev));
dev->parent_plat = NULL;
}
ret = uclass_unbind_device(dev);
......@@ -125,12 +125,12 @@ void device_free(struct udevice *dev)
int size;
if (dev->driver->priv_auto) {
free(dev->priv);
dev->priv = NULL;
free(dev_get_priv(dev));
dev_set_priv(dev, NULL);
}
size = dev->uclass->uc_drv->per_device_auto;
if (size) {
free(dev->uclass_priv);
free(dev_get_uclass_priv(dev));
dev->uclass_priv = NULL;
}
if (dev->parent) {
......@@ -140,7 +140,7 @@ void device_free(struct udevice *dev)
per_child_auto;
}
if (size) {
free(dev->parent_priv);
free(dev_get_parent_priv(dev));
dev->parent_priv = NULL;
}
}
......
......@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
int sdram_mmr_init_full(struct udevice *dev)
{
struct altera_sdram_plat *plat = dev->plat;
struct altera_sdram_plat *plat = dev_get_plat(dev);
struct altera_sdram_priv *priv = dev_get_priv(dev);
u32 i;
int ret;
......
......@@ -565,7 +565,7 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
static int altera_gen5_sdram_of_to_plat(struct udevice *dev)
{
struct altera_gen5_sdram_plat *plat = dev->plat;
struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
if (!plat->sdr)
......@@ -578,7 +578,7 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
{
int ret;
unsigned long sdram_size;
struct altera_gen5_sdram_plat *plat = dev->plat;
struct altera_gen5_sdram_plat *plat = dev_get_plat(dev);
struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
struct reset_ctl_bulk resets;
......
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