Commit 185f812c authored by Heinrich Schuchardt's avatar Heinrich Schuchardt
Browse files

doc: replace @return by Return:



Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;
Signed-off-by: default avatarHeinrich Schuchardt <heinrich.schuchardt@canonical.com>
parent 6a685753
......@@ -37,7 +37,7 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
* This operates at 1MHz and counts downwards. It will wrap about every
* hour (2^32 microseconds).
*
* @return current value of timer
* Return: current value of timer
*/
static unsigned long timer_get_us_down(void)
{
......
......@@ -217,14 +217,14 @@ struct ast2500_scu {
* ast_get_clk() - get a pointer to Clock Driver
*
* @devp, OUT - pointer to Clock Driver
* @return zero on success, error code (< 0) otherwise.
* Return: zero on success, error code (< 0) otherwise.
*/
int ast_get_clk(struct udevice **devp);
/**
* ast_get_scu() - get a pointer to SCU registers
*
* @return pointer to struct ast2500_scu on success, ERR_PTR otherwise
* Return: pointer to struct ast2500_scu on success, ERR_PTR otherwise
*/
void *ast_get_scu(void);
......
......@@ -84,7 +84,7 @@ struct ast_wdt {
* gets Reset Mode value from it.
*
* @flags: flags parameter passed into wdt_reset or wdt_start
* @return Reset Mode value
* Return: Reset Mode value
*/
u32 ast_reset_mode_from_flags(ulong flags);
......@@ -93,7 +93,7 @@ u32 ast_reset_mode_from_flags(ulong flags);
* gets Reset Mask value from it. Reset Mask is only supported on ast2500
*
* @flags: flags parameter passed into wdt_reset or wdt_start
* @return Reset Mask value
* Return: Reset Mask value
*/
u32 ast_reset_mask_from_flags(ulong flags);
......
......@@ -74,7 +74,7 @@ struct hi6220_pinmux1_regs {
* pull-up/down and drive strength.
*
* @param peripheral peripheral to be configured
* @return 0 if ok, -1 on error (e.g. unsupported peripheral)
* Return: 0 if ok, -1 on error (e.g. unsupported peripheral)
*/
int hi6220_pinmux_config(int peripheral);
......
......@@ -129,7 +129,7 @@ struct sysreset_reg {
*
* @input_rate: Input clock rate in Hz
* @output_rate: Output clock rate in Hz
* @return divisor register value to use
* Return: divisor register value to use
*/
static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
{
......@@ -144,14 +144,14 @@ static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
/**
* rockchip_get_cru() - get a pointer to the clock/reset unit registers
*
* @return pointer to registers, or -ve error on error
* Return: pointer to registers, or -ve error on error
*/
void *rockchip_get_cru(void);
/**
* rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
*
* @return pointer to registers, or -ve error on error
* Return: pointer to registers, or -ve error on error
*/
void *rockchip_get_pmucru(void);
......@@ -168,7 +168,7 @@ int rockchip_get_clk(struct udevice **devp);
* @pdev: clock udevice
* @reg_offset: the first offset in cru for softreset registers
* @reg_number: the reg numbers of softreset registers
* @return 0 success, or error value
* Return: 0 success, or error value
*/
int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
......
......@@ -42,21 +42,21 @@ extern void _start(void);
/**
* Works out the SOC/SKU type used for clocks settings
*
* @return SOC type - see TEGRA_SOC...
* Return: SOC type - see TEGRA_SOC...
*/
int tegra_get_chip_sku(void);
/**
* Returns the pure SOC (chip ID) from the HIDREV register
*
* @return SOC ID - see CHIPID_TEGRAxx...
* Return: SOC ID - see CHIPID_TEGRAxx...
*/
int tegra_get_chip(void);
/**
* Returns the SKU ID from the sku_info register
*
* @return SKU ID - see SKU_ID_Txx...
* Return: SKU ID - see SKU_ID_Txx...
*/
int tegra_get_sku_info(void);
......
......@@ -70,7 +70,7 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
* @param pllout pll output id
* @param rate desired output rate
*
* @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
* Return: 0 if ok, -1 on error (invalid clock id or no suitable divider)
*/
int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
unsigned rate);
......@@ -193,7 +193,7 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
* specific knowledge of system-level clock tree structure.
*
* @param periph_id peripheral to query
* @return clock ID of the peripheral's current parent clock
* Return: clock ID of the peripheral's current parent clock
*/
enum clock_id clock_get_periph_parent(enum periph_id periph_id);
......@@ -204,7 +204,7 @@ enum clock_id clock_get_periph_parent(enum periph_id periph_id);
* @param periph_id peripheral to start
* @param parent PLL id of required parent clock
* @param rate Required clock rate in Hz
* @return rate selected in Hz, or -1U if something went wrong
* Return: rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_start_periph_pll(enum periph_id periph_id,
enum clock_id parent, unsigned rate);
......@@ -217,7 +217,7 @@ unsigned clock_start_periph_pll(enum periph_id periph_id,
* @param periph_id peripheral to start
* @param parent PLL id of parent clock (used to calculate rate, you
* must know this!)
* @return clock rate of peripheral in Hz
* Return: clock rate of peripheral in Hz
*/
unsigned long clock_get_periph_rate(enum periph_id periph_id,
enum clock_id parent);
......@@ -233,7 +233,7 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
* @param rate Required clock rate in Hz
* @param extra_div value for the second-stage divisor (NULL if one is
not available)
* @return rate selected in Hz, or -1U if something went wrong
* Return: rate selected in Hz, or -1U if something went wrong
*/
unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
enum clock_id parent, unsigned rate, int *extra_div);
......@@ -242,7 +242,7 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
* Returns the clock rate of a specified clock, in Hz.
*
* @param parent PLL id of clock to check
* @return rate of clock in Hz
* Return: rate of clock in Hz
*/
unsigned clock_get_rate(enum clock_id clkid);
......@@ -265,21 +265,21 @@ void clock_ll_start_uart(enum periph_id periph_id);
*
* @param blob FDT blob to use
* @param node Node to look at
* @return peripheral ID, or PERIPH_ID_NONE if none
* Return: peripheral ID, or PERIPH_ID_NONE if none
*/
int clock_decode_periph_id(struct udevice *dev);
/**
* Checks if the oscillator bypass is enabled (XOBP bit)
*
* @return 1 if bypass is enabled, 0 if not
* Return: 1 if bypass is enabled, 0 if not
*/
int clock_get_osc_bypass(void);
/*
* Checks that clocks are valid and prints a warning if not
*
* @return 0 if ok, -1 on error
* Return: 0 if ok, -1 on error
*/
int clock_verify(void);
......@@ -310,7 +310,7 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
* @param mux_bits Set to number of bits in mux register
* @param divider_bits Set to the relevant MASK_BITS_* value
* @param type Set to the SoC-specific clock type
* @return 0 on success, -1 on error
* Return: 0 on success, -1 on error
*/
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type);
......@@ -324,7 +324,7 @@ int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
*
* @param periph_id peripheral to query
* @param source raw clock source mux value
* @return the CLOCK_ID_* value @source represents
* Return: the CLOCK_ID_* value @source represents
*/
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
......@@ -338,7 +338,7 @@ enum clock_id get_periph_clock_id(enum periph_id periph_id, int source);
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
* @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
* Return: mux value (0-4, or -1 if not found)
*/
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits);
......@@ -349,7 +349,7 @@ int get_periph_clock_source(enum periph_id periph_id,
* provided.
*
* @param clk_id Clock ID according to tegra30 device tree binding
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
* Return: peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
enum periph_id clk_id_to_periph_id(int clk_id);
......@@ -367,7 +367,7 @@ enum periph_id clk_id_to_periph_id(int clk_id);
* @param m PLL input divider(DIVN)
* @param p post divider(DIVP)
* @param cpcon base PLL charge pump(CPCON)
* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
* Return: 0 if ok, -1 on error (the requested PLL is incorrect and cannot
* be overridden), 1 if PLL is already correct
*/
int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
......@@ -416,7 +416,7 @@ extern struct periph_clk_init periph_clk_init_table[];
* Enable output clock for external peripherals
*
* @param clk_id Clock ID to output (1, 2 or 3)
* @return 0 if OK. -ve on error
* Return: 0 if OK. -ve on error
*/
int clock_external_output(int clk_id);
......
......@@ -21,7 +21,7 @@
*
* @param id Peripheral id
* @param config Configuration to use (FUNCMUX_...), 0 for default
* @return 0 if ok, -1 on error (e.g. incorrect id or config)
* Return: 0 if ok, -1 on error (e.g. incorrect id or config)
*/
int funcmux_select(enum periph_id id, int config);
......
......@@ -88,7 +88,7 @@ struct tegra_ivc {
* @ivc The IVC channel.
* @frame Pointer to be filled with the address of the frame to receive.
*
* @return 0 if a frame is available, else a negative error code.
* Return: 0 if a frame is available, else a negative error code.
*/
int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame);
......@@ -102,7 +102,7 @@ int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame);
*
* @ivc The IVC channel.
*
* @return 0 if OK, else a negative error code.
* Return: 0 if OK, else a negative error code.
*/
int tegra_ivc_read_advance(struct tegra_ivc *ivc);
......@@ -116,7 +116,7 @@ int tegra_ivc_read_advance(struct tegra_ivc *ivc);
* @ivc The IVC channel.
* @frame Pointer to be filled with the address of the frame to fill.
*
* @return 0 if a frame is available, else a negative error code.
* Return: 0 if a frame is available, else a negative error code.
*/
int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame);
......@@ -130,7 +130,7 @@ int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame);
*
* @ivc The IVC channel.
*
* @return 0 if OK, else a negative error code.
* Return: 0 if OK, else a negative error code.
*/
int tegra_ivc_write_advance(struct tegra_ivc *ivc);
......@@ -141,7 +141,7 @@ int tegra_ivc_write_advance(struct tegra_ivc *ivc);
*
* @ivc The IVC channel.
*
* @return 0 if the channel is ready for communication, or -EAGAIN if a
* Return: 0 if the channel is ready for communication, or -EAGAIN if a
* channel reset is in progress.
*/
int tegra_ivc_channel_notified(struct tegra_ivc *ivc);
......@@ -167,7 +167,7 @@ void tegra_ivc_channel_reset(struct tegra_ivc *ivc);
* @nframes Number of frames in each shared memory buffer.
* @frame_size Size of each frame.
*
* @return 0 if OK, else a negative error code.
* Return: 0 if OK, else a negative error code.
*/
int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base,
uint32_t nframes, uint32_t frame_size,
......
......@@ -12,7 +12,7 @@ void invalidate_dcache(void);
/**
* tegra_board_id() - Get the board iD
*
* @return a board ID, or -ve on error
* Return: a board ID, or -ve on error
*/
int tegra_board_id(void);
......@@ -20,14 +20,14 @@ int tegra_board_id(void);
* tegra_lcd_pmic_init() - Set up the PMIC for a board
*
* @board_id: Board ID which may be used to select LCD type
* @return 0 if OK, -ve on error
* Return: 0 if OK, -ve on error
*/
int tegra_lcd_pmic_init(int board_id);
/**
* nvidia_board_init() - perform any board-specific init
*
* @return 0 if OK, -ve on error
* Return: 0 if OK, -ve on error
*/
int nvidia_board_init(void);
......
......@@ -150,7 +150,7 @@ struct i2c_ctlr {
/**
* Returns the bus number of the DVC controller
*
* @return number of bus, or -1 if there is no DVC active
* Return: number of bus, or -1 if there is no DVC active
*/
int tegra_i2c_get_dvc_bus(struct udevice **busp);
......
......@@ -121,7 +121,7 @@ union scratch3_reg {
/**
* Save warmboot memory settings for a later resume
*
* @return 0 if ok, -1 on error
* Return: 0 if ok, -1 on error
*/
int warmboot_save_sdram_params(void);
......
......@@ -16,14 +16,14 @@
*
* @param blob Device tree blob
* @param default_lcd_base Default address of LCD frame buffer
* @return 0 if ok, -1 on error (unsupported bits per pixel)
* Return: 0 if ok, -1 on error (unsupported bits per pixel)
*/
int tegra_display_probe(const void *blob, void *default_lcd_base);
/**
* Return the current display configuration
*
* @return pointer to display configuration, or NULL if there is no valid
* Return: pointer to display configuration, or NULL if there is no valid
* config
*/
struct fdt_disp_config *tegra_display_get_config(void);
......
......@@ -81,7 +81,7 @@ struct emc_ctlr {
*
* @param blob Device tree blob
* @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
* @return 0 if ok, else -ve error code (look in emc.c to decode it)
* Return: 0 if ok, else -ve error code (look in emc.c to decode it)
*/
int tegra_set_emc(const void *blob, unsigned rate);
......@@ -89,7 +89,7 @@ int tegra_set_emc(const void *blob, unsigned rate);
* Get a pointer to the EMC controller from the device tree.
*
* @param blob Device tree blob
* @return pointer to EMC controller
* Return: pointer to EMC controller
*/
struct emc_ctlr *emc_get_controller(const void *blob);
......
......@@ -43,7 +43,7 @@ extern const struct gpio_bank *const omap_gpio_bank;
* Check if gpio is valid.
*
* @param gpio GPIO number
* @return 1 if ok, 0 on error
* Return: 1 if ok, 0 on error
*/
int gpio_is_valid(int gpio);
#endif
......
......@@ -10,7 +10,7 @@
* bcm2835_power_on_module() - power on an SoC module
*
* @module: ID of module to power on (BCM2835_MBOX_POWER_DEVID_...)
* @return 0 if OK, -EIO on error
* Return: 0 if OK, -EIO on error
*/
int bcm2835_power_on_module(u32 module);
......@@ -18,7 +18,7 @@ int bcm2835_power_on_module(u32 module);
* bcm2835_get_mmc_clock() - get the frequency of the MMC clock
*
* @clock_id: ID of clock to get frequency for
* @return clock frequency, or -ve on error
* Return: clock frequency, or -ve on error
*/
int bcm2835_get_mmc_clock(u32 clock_id);
......@@ -27,7 +27,7 @@ int bcm2835_get_mmc_clock(u32 clock_id);
*
* @widthp: Returns the width in pixels
* @heightp: Returns the height in pixels
* @return 0 if OK, -ve on error
* Return: 0 if OK, -ve on error
*/
int bcm2835_get_video_size(int *widthp, int *heightp);
......@@ -42,7 +42,7 @@ int bcm2835_get_video_size(int *widthp, int *heightp);
* @fb_basep: Returns base address of frame buffer
* @fb_sizep: Returns size of frame buffer
* @pitchp: Returns number of bytes in each frame buffer line
* @return 0 if OK, -ve on error
* Return: 0 if OK, -ve on error
*/
int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
int pixel_order, int alpha_mode, ulong *fb_basep,
......@@ -51,7 +51,7 @@ int bcm2835_set_video_params(int *widthp, int *heightp, int depth_bpp,
/**
* bcm2711_load_vl805_firmware() - get vl805's firmware loaded
*
* @return 0 if OK, -EIO on error
* Return: 0 if OK, -EIO on error
*/
int bcm2711_notify_vl805_reset(void);
......
......@@ -1403,7 +1403,7 @@ int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
* @param target_freq Desired clock frequency in Hz
* @param best_fine_scalar Pointer to store the fine stage divisor
*
* @return best_main_scalar Main scalar for desired frequency or -1 if none
* Return: best_main_scalar Main scalar for desired frequency or -1 if none
* found
*/
static int clock_calc_best_scalar(unsigned int main_scaler_bits,
......
......@@ -141,7 +141,7 @@ struct mem_timings {
*
* This function can be called from SPL or the main U-Boot.
*
* @return pointer to the memory timings that we should use
* Return: pointer to the memory timings that we should use
*/
struct mem_timings *clock_get_mem_timings(void);
......
......@@ -40,7 +40,7 @@ void system_clock_init(void);
/*
* Init subsystems according to the reset status
*
* @return 0 for a normal boot, non-zero for a resume
* Return: 0 for a normal boot, non-zero for a resume
*/
int do_lowlevel_init(void);
......
......@@ -253,7 +253,7 @@ static const unsigned int test_pattern[] = {
* @param ch DMC channel number
* @param byte_lane which DQS byte offset,
* possible values are 0,1,2,3
* @return TRUE if memory was good, FALSE if not.
* Return: TRUE if memory was good, FALSE if not.
*/
static bool dmc_valid_window_test_vector(int ch, int byte_lane)
{
......@@ -323,7 +323,7 @@ static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
* representations of 0.
*
* @param b The byte to convert in two's complement.
* @return The 7-bit value + sign bit.
* Return: The 7-bit value + sign bit.
*/
unsigned char make_signed_byte(signed char b)
......
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