Commit 4652bef1 authored by Tom Rini's avatar Tom Rini
Browse files

arm: Remove apf27 board



This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
parent be3dec48
......@@ -561,11 +561,6 @@ config ARCH_MVEBU
select SPI
imply CMD_DM
config TARGET_APF27
bool "Support apf27"
select CPU_ARM926EJS
select SUPPORT_SPL
config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
......@@ -1969,7 +1964,6 @@ source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
......
if TARGET_APF27
config SYS_BOARD
default "apf27"
config SYS_VENDOR
default "armadeus"
config SYS_SOC
default "mx27"
config SYS_CONFIG_NAME
default "apf27"
endif
APF27 BOARD
M: Philippe Reynes <tremyfr@yahoo.fr>
M: Eric Jarrige <eric.jarrige@armadeus.org>
S: Maintained
F: board/armadeus/apf27/
F: include/configs/apf27.h
F: configs/apf27_defconfig
#
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2012-2013
# Eric Jarrige <eric.jarrige@armadeus.org>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := apf27.o
obj-y += lowlevel_init.o
obj-$(CONFIG_FPGA) += fpga.o
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
*
* based on the files by
* Sascha Hauer, Pengutronix
*/
#include <common.h>
#include <hang.h>
#include <init.h>
#include <asm/global_data.h>
#include <jffs2/jffs2.h>
#include <nand.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
#include "apf27.h"
#include "fpga.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Fuse bank 1 row 8 is "reserved for future use" and therefore available for
* customer use. The APF27 board uses this fuse to store the board revision:
* 0: initial board revision
* 1: first revision - Presence of the second RAM chip on the board is blown in
* fuse bank 1 row 9 bit 0 - No hardware change
* N: to be defined
*/
static u32 get_board_rev(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
return readl(&iim->bank[1].fuse_regs[8]);
}
/*
* Fuse bank 1 row 9 is "reserved for future use" and therefore available for
* customer use. The APF27 board revision 1 uses the bit 0 to permanently store
* the presence of the second RAM chip
* 0: AFP27 with 1 RAM of 64 MiB
* 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
*/
static int get_num_ram_bank(void)
{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
int nr_dram_banks = 1;
if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
else
nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
return nr_dram_banks;
}
static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
u32 puen, u32 gius)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
writel(gpio_dr, &regs->port[port].gpio_dr);
writel(ocr1, &regs->port[port].ocr1);
writel(ocr2, &regs->port[port].ocr2);
writel(iconfa1, &regs->port[port].iconfa1);
writel(iconfa2, &regs->port[port].iconfa2);
writel(iconfb1, &regs->port[port].iconfb1);
writel(iconfb2, &regs->port[port].iconfb2);
writel(icr1, &regs->port[port].icr1);
writel(icr2, &regs->port[port].icr2);
writel(imr, &regs->port[port].imr);
writel(gpio_dir, &regs->port[port].gpio_dir);
writel(gpr, &regs->port[port].gpr);
writel(puen, &regs->port[port].puen);
writel(gius, &regs->port[port].gius);
}
#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
ACFG_GIUS_##n##_VAL)
static void apf27_iomux_init(void)
{
APF27_PORT_INIT(A);
APF27_PORT_INIT(B);
APF27_PORT_INIT(C);
APF27_PORT_INIT(D);
APF27_PORT_INIT(E);
APF27_PORT_INIT(F);
}
static int apf27_devices_init(void)
{
int i;
unsigned int mode[] = {
PC5_PF_I2C2_DATA,
PC6_PF_I2C2_CLK,
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
#ifdef CONFIG_MXC_UART
mx27_uart1_init_pins();
#endif
#ifdef CONFIG_FEC_MXC
mx27_fec_init_pins();
#endif
#ifdef CONFIG_MMC_MXC
mx27_sd2_init_pins();
imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
gpio_request(PC_PWRON, "pc_pwron");
gpio_set_value(PC_PWRON, 1);
#endif
return 0;
}
static void apf27_setup_csx(void)
{
struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
writel(ACFG_CS0U_VAL, &weim->cs0u);
writel(ACFG_CS0L_VAL, &weim->cs0l);
writel(ACFG_CS0A_VAL, &weim->cs0a);
writel(ACFG_CS1U_VAL, &weim->cs1u);
writel(ACFG_CS1L_VAL, &weim->cs1l);
writel(ACFG_CS1A_VAL, &weim->cs1a);
writel(ACFG_CS2U_VAL, &weim->cs2u);
writel(ACFG_CS2L_VAL, &weim->cs2l);
writel(ACFG_CS2A_VAL, &weim->cs2a);
writel(ACFG_CS3U_VAL, &weim->cs3u);
writel(ACFG_CS3L_VAL, &weim->cs3l);
writel(ACFG_CS3A_VAL, &weim->cs3a);
writel(ACFG_CS4U_VAL, &weim->cs4u);
writel(ACFG_CS4L_VAL, &weim->cs4l);
writel(ACFG_CS4A_VAL, &weim->cs4a);
writel(ACFG_CS5U_VAL, &weim->cs5u);
writel(ACFG_CS5L_VAL, &weim->cs5l);
writel(ACFG_CS5A_VAL, &weim->cs5a);
writel(ACFG_EIM_VAL, &weim->eim);
}
static void apf27_setup_port(void)
{
struct system_control_regs *system =
(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
writel(ACFG_FMCR_VAL, &system->fmcr);
}
int board_init(void)
{
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
apf27_setup_csx();
apf27_setup_port();
apf27_iomux_init();
apf27_devices_init();
#if defined(CONFIG_FPGA)
APF27_init_fpga();
#endif
return 0;
}
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
if (get_num_ram_bank() > 1)
gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
return 0;
}
int dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
if (get_num_ram_bank() > 1)
gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
else
gd->bd->bi_dram[1].size = 0;
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
ulong ramtop;
if (get_num_ram_bank() > 1)
ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
PHYS_SDRAM_2_SIZE);
else
ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return ramtop;
}
int checkboard(void)
{
printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
return 0;
}
#ifdef CONFIG_SPL_BUILD
inline void hang(void)
{
for (;;)
;
}
void board_init_f(ulong bootflag)
{
/*
* copy ourselves from where we are running to where we were
* linked at. Use ulong pointers as all addresses involved
* are 4-byte-aligned.
*/
ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
for (dst = start_ptr; dst < end_ptr; dst++)
*dst = *(dst+(run_ptr-link_ptr));
/*
* branch to nand_boot's link-time address.
*/
asm volatile("ldr pc, =nand_boot");
}
#endif /* CONFIG_SPL_BUILD */
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
*/
#ifndef __APF27_H
#define __APF27_H
/* FPGA program pin configuration */
#define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */
#define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */
#define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */
#define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */
#define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */
#define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */
#define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */
#define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */
#define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */
#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
/* MMC pin */
#define PC_PWRON (GPIO_PORTF | 16)
/*
* MPU CLOCK source before PLL
* ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
*/
#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
#define ACFG_MPCTL1_VAL 0
#define CONFIG_MPLL_FREQ 399
#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
#define ACFG_SPCTL1_VAL 0
#define CONFIG_SPLL_FREQ 300 /* MHz */
/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
#define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */
#define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
#define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
#define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
#define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
#define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */
#define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */
#define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */
#define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */
#define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */
#define CONFIG_CLK0_EN 1 /* CLK0 enabled */
/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
#define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */
/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
#define CONFIG_USB_FREQ 60 /* 60 MHz */
/*
* SDRAM
*/
#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
/* micron 64MB */
#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
* cycle delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
* 2=quater 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
#if (ACFG_SDRAM_MBYTE_SYZE == 128)
/* micron 128MB */
#define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read
* cycle delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half
* 2=quater 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
#if (ACFG_SDRAM_MBYTE_SYZE == 256)
/* micron 256MB */
#define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11
* column address bits
*/
#define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13
* row address bits
*/
#define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048
* 2=4096 3=8192 refresh
*/
#define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power
* down delay
*/
#define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle
* delay > 0
*/
#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
#define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register
* cycle delay 1..4
*/
#define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck
* SDRAM: 0=1ck 1=2ck
*/
#define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */
#define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */
#define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */
#define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC
* refresh to command)
*/
#define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time
* estimated fo CL=1
* 0=force 3 for lpddr
*/
#define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater
* 3=Eighth 4=Sixteenth
*/
#define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength
* 1=half
* 2=quater
* 3=Eighth
*/
#define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
#define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access
* 0 = Burst mode
*/
#endif
/*
* External interface
*/
/*
* CSCRxU_VAL:
* 31| x | x | x x |x x x x| x x | x | x |x x x x|16
* |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL |
*
* 15| x x | x x x x x x | x | x x x x | x x x x |0
* | CNC | WSC |EW | WWS | EDC |
*
* CSCRxL_VAL:
* 31| x x x x | x x x x | x x x x | x x x x |16
* | OEA | OEN | EBWA | EBWN |
* 15|x x x x| x |x x x |x x x x| x | x | x | x | 0
* | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN|
*
* CSCRxA_VAL:
* 31| x x x x | x x x x | x x x x | x x x x |16
* | EBRA | EBRN | RWA | RWN |
* 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0
* |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
*/
/* CS0 configuration for 16 bit nor flash */
#define ACFG_CS0U_VAL 0x0000CC03
#define ACFG_CS0L_VAL 0xa0330D01
#define ACFG_CS0A_VAL 0x00220800
#define ACFG_CS1U_VAL 0x00000f00
#define ACFG_CS1L_VAL 0x00000D01
#define ACFG_CS1A_VAL 0
#define ACFG_CS2U_VAL 0
#define ACFG_CS2L_VAL 0
#define ACFG_CS2A_VAL 0
#define ACFG_CS3U_VAL 0
#define ACFG_CS3L_VAL 0
#define ACFG_CS3A_VAL 0
#define ACFG_CS4U_VAL 0
#define ACFG_CS4L_VAL 0
#define ACFG_CS4A_VAL 0
/* FPGA 16 bit data bus */
#define ACFG_CS5U_VAL 0x00000600
#define ACFG_CS5L_VAL 0x00000D01
#define ACFG_CS5A_VAL 0
#define ACFG_EIM_VAL 0x00002200
/*
* FPGA specific settings
*/
/* CLKO */
#define ACFG_CCSR_VAL 0x00000305
/* drive strength CLKO set to 2 */
#define ACFG_DSCR10_VAL 0x00020000
/* drive strength A1..A12 set to 2 */
#define ACFG_DSCR3_VAL 0x02AAAAA8
/* drive strength ctrl */
#define ACFG_DSCR7_VAL 0x00020880
/* drive strength data */
#define ACFG_DSCR2_VAL 0xAAAAAAAA
/*
* Default configuration for GPIOs and peripherals
*/
#define ACFG_DDIR_A_VAL 0x00000000
#define ACFG_OCR1_A_VAL 0x00000000
#define ACFG_OCR2_A_VAL 0x00000000
#define ACFG_ICFA1_A_VAL 0xFFFFFFFF
#define ACFG_ICFA2_A_VAL 0xFFFFFFFF
#define ACFG_ICFB1_A_VAL 0xFFFFFFFF
#define ACFG_ICFB2_A_VAL 0xFFFFFFFF
#define ACFG_DR_A_VAL 0x00000000
#define ACFG_GIUS_A_VAL 0xFFFFFFFF
#define ACFG_ICR1_A_VAL 0x00000000
#define ACFG_ICR2_A_VAL 0x00000000
#define ACFG_IMR_A_VAL 0x00000000
#define ACFG_GPR_A_VAL 0x00000000
#define ACFG_PUEN_A_VAL 0xFFFFFFFF
#define ACFG_DDIR_B_VAL 0x00000000
#define ACFG_OCR1_B_VAL 0x00000000
#define ACFG_OCR2_B_VAL 0x00000000
#define ACFG_ICFA1_B_VAL 0xFFFFFFFF
#define ACFG_ICFA2_B_VAL 0xFFFFFFFF
#define ACFG_ICFB1_B_VAL 0xFFFFFFFF
#define ACFG_ICFB2_B_VAL 0xFFFFFFFF
#define ACFG_DR_B_VAL 0x00000000
#define ACFG_GIUS_B_VAL 0xFF3FFFF0
#define ACFG_ICR1_B_VAL 0x00000000
#define ACFG_ICR2_B_VAL 0x00000000
#define ACFG_IMR_B_VAL 0x00000000
#define ACFG_GPR_B_VAL 0x00000000
#define ACFG_PUEN_B_VAL 0xFFFFFFFF
#define ACFG_DDIR_C_VAL 0x00000000
#define ACFG_OCR1_C_VAL 0x00000000
#define ACFG_OCR2_C_VAL 0x00000000
#define ACFG_ICFA1_C_VAL 0xFFFFFFFF
#define ACFG_ICFA2_C_VAL 0xFFFFFFFF
#define ACFG_ICFB1_C_VAL 0xFFFFFFFF
#define ACFG_ICFB2_C_VAL 0xFFFFFFFF
#define ACFG_DR_C_VAL 0x00000000
#define ACFG_GIUS_C_VAL 0xFFFFC07F