Commit 4bc0104c authored by Weijie Gao's avatar Weijie Gao Committed by Daniel Schwierzeck
Browse files

mips: mtmips: add support for MediaTek MT7621 SoC

This patch adds support for MediaTek MT7621 SoC.
All files are dedicated for u-boot.

The default build target is u-boot-mt7621.bin.

The specification of this chip:
https://www.mediatek.com/products/homenetworking/mt7621



Reviewed-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: default avatarWeijie Gao <weijie.gao@mediatek.com>
parent 2948d9cf
......@@ -4,6 +4,11 @@ head-y := arch/mips/cpu/start.o
ifeq ($(CONFIG_SPL_BUILD),y)
head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o
head-$(CONFIG_SOC_MT7621) := arch/mips/mach-mtmips/mt7621/spl/start.o
endif
ifeq ($(CONFIG_TPL_BUILD),y)
head-$(CONFIG_SOC_MT7621) := arch/mips/mach-mtmips/mt7621/tpl/start.o
endif
libs-y += arch/mips/cpu/
......
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc. All rights reserved.
*
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#include <linux/stringify.h>
/ {
binman: binman {
multiple-images;
};
};
&sysc {
u-boot,dm-pre-reloc;
};
&reboot {
u-boot,dm-pre-reloc;
};
&clkctrl {
u-boot,dm-pre-reloc;
};
&rstctrl {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&uart0 {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};
&uart2 {
u-boot,dm-pre-reloc;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
stage_bin {
filename = "mt7621_stage_sram.bin";
type = "blob-ext";
};
};
spl-img {
filename = "u-boot-spl-ddr.img";
mkimage {
#ifdef CONFIG_MT7621_BOOT_FROM_NAND
args = "-T", "mtk_image", "-n", "mt7621=1",
"-a", __stringify(CONFIG_SPL_TEXT_BASE),
"-e", __stringify(CONFIG_SPL_TEXT_BASE);
#else
args = "-A", "mips", "-T", "standalone", "-O", "u-boot",
"-C", "none", "-n", "MT7621 U-Boot SPL",
"-a", __stringify(CONFIG_SPL_TEXT_BASE),
"-e", __stringify(CONFIG_SPL_TEXT_BASE);
#endif
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
mt7621-uboot {
filename = "u-boot-mt7621.bin";
pad-byte = <0xff>;
#ifndef CONFIG_MT7621_BOOT_FROM_NAND
u-boot-tpl {
align-end = <4>;
filename = "u-boot-tpl.bin";
};
#endif
spl {
#ifdef CONFIG_MT7621_BOOT_FROM_NAND
align-end = <0x1000>;
#endif
filename = "u-boot-spl-ddr.img";
type = "blob";
};
u-boot {
filename = "u-boot-lzma.img";
type = "blob";
};
};
};
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022 MediaTek Inc. All rights reserved.
*
* Author: Weijie Gao <weijie.gao@mediatek.com>
*/
#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/reset/mt7621-reset.h>
#include <dt-bindings/phy/phy.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7621-soc";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips1004Kc";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "mips,mips1004Kc";
reg = <1>;
};
};
clk48m: clk48m {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
clk50m: clk50m {
compatible = "fixed-clock";
clock-frequency = <50000000>;
#clock-cells = <0>;
};
sysc: sysctrl@1e000000 {
compatible = "mediatek,mt7621-sysc", "syscon";
reg = <0x1e000000 0x100>;
clkctrl: clock-controller@1e000030 {
compatible = "mediatek,mt7621-clk";
mediatek,memc = <&memc>;
#clock-cells = <1>;
};
};
rstctrl: reset-controller@1e000034 {
compatible = "mediatek,mtmips-reset";
reg = <0x1e000034 0x4>;
#reset-cells = <1>;
};
reboot: resetctl-reboot {
compatible = "resetctl-reboot";
resets = <&rstctrl RST_SYS>;
reset-names = "sysreset";
};
memc: memctrl@1e005000 {
compatible = "mediatek,mt7621-memc", "syscon";
reg = <0x1e005000 0x1000>;
};
pinctrl: pinctrl@1e000060 {
compatible = "mediatek,mt7621-pinctrl";
reg = <0x1e000048 0x30>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pin_state {
};
uart1_pins: uart1_pins {
groups = "uart1";
function = "uart";
};
uart2_pins: uart2_pins {
groups = "uart2";
function = "uart";
};
uart3_pins: uart3_pins {
groups = "uart3";
function = "uart";
};
sdxc_pins: sdxc_pins {
groups = "sdxc";
function = "sdxc";
};
spi_pins: spi_pins {
groups = "spi";
function = "spi";
};
eth_pins: eth_pins {
mdio_pins {
groups = "mdio";
function = "mdio";
};
rgmii1_pins {
groups = "rgmii1";
function = "rgmii";
};
esw_pins {
groups = "esw int";
function = "esw int";
};
mdio_pconf {
groups = "mdio";
drive-strength = <2>;
};
};
};
watchdog: watchdog@1e000100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x1e000100 0x40>;
resets = <&rstctrl RST_TIMER>;
reset-names = "wdt";
status = "disabled";
};
gpio: gpio@1e000600 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mtk,mt7621-gpio";
reg = <0x1e000600 0x100>;
resets = <&rstctrl RST_PIO>;
reset-names = "pio";
gpio0: bank@0 {
reg = <0>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
gpio1: bank@1 {
reg = <1>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
gpio2: bank@2 {
reg = <2>;
compatible = "mtk,mt7621-gpio-bank";
gpio-controller;
#gpio-cells = <2>;
};
};
spi: spi@1e000b00 {
compatible = "ralink,mt7621-spi";
reg = <0x1e000b00 0x40>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&spi_pins>;
resets = <&rstctrl RST_SPI>;
reset-names = "spi";
clocks = <&clkctrl MT7621_CLK_SPI>;
#address-cells = <1>;
#size-cells = <0>;
};
uart0: uart1@1e000c00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0x1e000c00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
clocks = <&clkctrl MT7621_CLK_UART1>;
resets = <&rstctrl RST_UART1>;
reg-shift = <2>;
};
uart1: uart2@1e000d00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0x1e000d00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
clocks = <&clkctrl MT7621_CLK_UART2>;
resets = <&rstctrl RST_UART2>;
reg-shift = <2>;
status = "disabled";
};
uart2: uart3@1e000e00 {
compatible = "mediatek,hsuart", "ns16550a";
reg = <0x1e000e00 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
clocks = <&clkctrl MT7621_CLK_UART3>;
resets = <&rstctrl RST_UART3>;
reg-shift = <2>;
status = "disabled";
};
eth: eth@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x20000>;
mediatek,ethsys = <&sysc>;
pinctrl-names = "default";
pinctrl-0 = <&eth_pins>;
resets = <&rstctrl RST_FE>, <&rstctrl RST_GMAC>, <&rstctrl RST_MCM>;
reset-names = "fe", "gmac", "mcm";
clocks = <&clkctrl MT7621_CLK_GDMA>,
<&clkctrl MT7621_CLK_ETH>;
clock-names = "gmac", "fe";
#address-cells = <1>;
#size-cells = <0>;
mediatek,gmac-id = <0>;
phy-mode = "rgmii";
mediatek,switch = "mt7530";
mediatek,mcm;
fixed-link {
speed = <1000>;
full-duplex;
};
};
mmc: mmc@1e130000 {
compatible = "mediatek,mt7621-mmc";
reg = <0x1e130000 0x4000>;
status = "disabled";
bus-width = <4>;
builtin-cd = <1>;
r_smpl = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdxc_pins>;
clocks = <&clk50m>, <&clkctrl MT7621_CLK_SHXC>;
clock-names = "source", "hclk";
resets = <&rstctrl RST_SDXC>;
};
ssusb: usb@1e1c0000 {
compatible = "mediatek,mt7621-xhci", "mediatek,mtk-xhci";
reg = <0x1e1c0000 0x1000>, <0x1e1d0700 0x100>;
reg-names = "mac", "ippc";
clocks = <&clk48m>, <&clk48m>;
clock-names = "sys_ck", "ref_ck";
phys = <&u2port0 PHY_TYPE_USB2>,
<&u3port0 PHY_TYPE_USB3>,
<&u2port1 PHY_TYPE_USB2>;
status = "disabled";
};
u3phy: usb-phy@1e1d0000 {
compatible = "mediatek,mt7621-u3phy",
"mediatek,generic-tphy-v1";
reg = <0x1e1d0000 0x700>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
status = "disabled";
u2port0: usb-phy@1e1d0800 {
reg = <0x1e1d0800 0x0100>;
#phy-cells = <1>;
clocks = <&clk48m>;
clock-names = "ref";
};
u3port0: usb-phy@1e1d0900 {
reg = <0x1e1d0900 0x0100>;
#phy-cells = <1>;
};
u2port1: usb-phy@1e1d1000 {
reg = <0x1e1d1000 0x0100>;
#phy-cells = <1>;
clocks = <&clk48m>;
clock-names = "ref";
};
};
i2c: i2c@1e000900 {
compatible = "i2c-gpio";
status = "disabled";
i2c-gpio,delay-us = <3>;
gpios = <&gpio0 3 1>, /* PIN3 as SDA */
<&gpio0 4 1>; /* PIN4 as CLK */
#address-cells = <1>;
#size-cells = <0>;
};
};
......@@ -9,6 +9,7 @@ config SYS_MALLOC_F_LEN
config SYS_SOC
default "mt7620" if SOC_MT7620
default "mt7621" if SOC_MT7621
default "mt7628" if SOC_MT7628
config SYS_DCACHE_SIZE
......@@ -18,25 +19,45 @@ config SYS_DCACHE_LINE_SIZE
default 32
config SYS_ICACHE_SIZE
default 65536
default 65536 if SOC_MT7620 || SOC_MT7628
default 32768 if SOC_MT7621
config SYS_ICACHE_LINE_SIZE
default 32
config SYS_SCACHE_LINE_SIZE
default 32 if SOC_MT7621
config SYS_TEXT_BASE
default 0x9c000000 if !SPL
default 0x80200000 if SPL
default 0x9c000000 if !SPL && !SOC_MT7621
default 0x80200000 if SPL || SOC_MT7621
config SPL_TEXT_BASE
default 0x9c000000
default 0x9c000000 if !SOC_MT7621
default 0x80100000 if SOC_MT7621
config SPL_SIZE_LIMIT
default 0x30000 if SOC_MT7621
config TPL_TEXT_BASE
default 0xbfc00000 if SOC_MT7621
config TPL_MAX_SIZE
default 4096 if SOC_MT7621
config SPL_PAYLOAD
default "u-boot-lzma.img" if SPL_LZMA
config BUILD_TARGET
default "u-boot-with-spl.bin" if SPL
default "u-boot-with-spl.bin" if SPL && !SOC_MT7621
default "u-boot-lzma.img" if SOC_MT7621
default "u-boot.bin"
config MAX_MEM_SIZE
int
default 256 if SOC_MT7620 || SOC_MT7628
default 512 if SOC_MT7621
choice
prompt "MediaTek MIPS SoC select"
......@@ -55,6 +76,23 @@ config SOC_MT7620
help
This supports MediaTek MT7620.
config SOC_MT7621
bool "MT7621"
select MIPS_CM
select MIPS_L2_CACHE
select SYS_CACHE_SHIFT_5
select SYS_MIPS_CACHE_INIT_RAM_LOAD
select PINCTRL_MT7621
select MTK_SERIAL
select REGMAP
select SYSCON
select BINMAN
select SUPPORT_TPL
select SPL_LOADER_SUPPORT if SPL
select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
help
This supports MediaTek MT7621.
config SOC_MT7628
bool "MT7628"
select SYS_CACHE_SHIFT_5
......@@ -80,6 +118,7 @@ config SOC_MT7628
endchoice
source "arch/mips/mach-mtmips/mt7620/Kconfig"
source "arch/mips/mach-mtmips/mt7621/Kconfig"
source "arch/mips/mach-mtmips/mt7628/Kconfig"
endmenu
# SPDX-License-Identifier: GPL-2.0+
obj-y += cpu.o
ifneq ($(CONFIG_SOC_MT7621),y)
obj-y += ddr_init.o
obj-y += ddr_cal.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
obj-$(CONFIG_SOC_MT7620) += mt7620/
obj-$(CONFIG_SOC_MT7621) += mt7621/
obj-$(CONFIG_SOC_MT7628) += mt7628/
......@@ -16,7 +16,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M);
gd->ram_size = get_ram_size((void *)KSEG1, CONFIG_MAX_MEM_SIZE << 20);
return 0;
}
......
if SOC_MT7621
menu "CPU & DDR configuration"
config MT7621_CPU_FREQ
int "CPU Frequency (MHz)"
range 400 1200
default 880
choice
prompt "DRAM Frequency"
default MT7621_DRAM_FREQ_1200
config MT7621_DRAM_FREQ_400
bool "400MHz"
config MT7621_DRAM_FREQ_800
bool "800MHz"
config MT7621_DRAM_FREQ_1066
bool "1066MHz"
config MT7621_DRAM_FREQ_1200
bool "1200MHz"
endchoice
choice
prompt "DDR2 timing parameters"
default MT7621_DRAM_DDR2_1024M
config MT7621_DRAM_DDR2_512M
bool "64MB"
config MT7621_DRAM_DDR2_1024M
bool "128MB"
config MT7621_DRAM_DDR2_512M_W9751G6KB_A02_1066MHZ
bool "W9751G6KB_A02 @ 1066MHz (64MB)"
config MT7621_DRAM_DDR2_1024M_W971GG6KB25_800MHZ
bool "W971GG6KB25 @ 800MHz (128MB)"
config MT7621_DRAM_DDR2_1024M_W971GG6KB18_1066MHZ
bool "W971GG6KB18 @ 1066MHz (128MB)"
endchoice
choice
prompt "DDR3 timing parameters"
default MT7621_DRAM_DDR3_2048M
config MT7621_DRAM_DDR3_1024M
bool "128MB"
config MT7621_DRAM_DDR3_1024M_KGD
bool "128MB KGD (MT7621DA)"
config MT7621_DRAM_DDR3_2048M
bool "256MB"
config MT7621_DRAM_DDR3_4096M
bool "512MB"