Commit 720620e6 authored by Tom Rini's avatar Tom Rini
Browse files

Merge tag 'v2021.01-rc5' into next



Prepare v2021.01-rc5
Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
parents c86b1807 62b07b51
Pipeline #5762 passed with stages
in 58 minutes and 26 seconds
......@@ -30,7 +30,10 @@ Jagan Teki <jaganna@xilinx.com>
Jagan Teki <jagannadh.teki@gmail.com>
Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@linaro.org>
Igor Opaniuk <igor.opaniuk@gmail.com> <igor.opaniuk@toradex.com>
Markus Klotzbuecher <mk@denx.de>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
Rajeshwari Shinde <rajeshwari.s@samsung.com>
......
This diff is collapsed.
......@@ -195,6 +195,7 @@ F: drivers/watchdog/cortina_wdt.c
F: drivers/serial/serial_cortina.c
F: drivers/led/led_cortina.c
F: drivers/mmc/ca_dw_mmc.c
F: drivers/spi/ca_sflash.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
......@@ -385,7 +386,7 @@ F: drivers/smem/msm_smem.c
F: drivers/usb/host/ehci-msm.c
ARM STI
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
F: arch/arm/mach-sti/
......@@ -411,8 +412,8 @@ F: arch/arm/cpu/arm926ejs/spear/
F: arch/arm/include/asm/arch-spear/
ARM STM STM32MP
M: Patrick Delaunay <patrick.delaunay@st.com>
M: Patrice Chotard <patrice.chotard@st.com>
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
M: Patrice Chotard <patrice.chotard@foss.st.com>
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm.git
S: Maintained
......@@ -679,6 +680,7 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
F: doc/api/efi.rst
F: doc/uefi/*
F: doc/usage/bootefi.rst
F: drivers/rtc/emul_rtc.c
F: include/capitalization.h
F: include/charset.h
......@@ -696,6 +698,7 @@ F: test/unicode_ut.c
F: cmd/bootefi.c
F: cmd/efidebug.c
F: cmd/nvedit_efi.c
F: tools/efivar.py
F: tools/file2include.c
EFI VARIABLES VIA OP-TEE
......@@ -758,6 +761,7 @@ T: git https://gitlab.denx.de/u-boot/u-boot.git
F: common/log*
F: cmd/log.c
F: doc/develop/logging.rst
F: include/log.h
F: lib/getopt.c
F: test/log/
F: test/py/tests/test_log.py
......@@ -799,6 +803,7 @@ F: drivers/watchdog/cortina_wdt.c
F: drivers/serial/serial_cortina.c
F: drivers/led/led_cortina.c
F: drivers/mmc/ca_dw_mmc.c
F: drivers/spi/ca_sflash.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
......
......@@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 01
SUBLEVEL =
EXTRAVERSION = -rc3
EXTRAVERSION = -rc5
NAME =
# *DOCUMENTATION*
......
......@@ -90,14 +90,15 @@
};
spi0: spi@0 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,axs10x-spi", "snps,dw-apb-ssi";
reg = <0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&apbclk>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
......
......@@ -128,14 +128,15 @@
};
spi0: spi@f0020000 {
compatible = "snps,dw-apb-ssi";
compatible = "snps,hsdk-spi", "snps,dw-apb-ssi";
reg = <0xf0020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <4000000>;
clocks = <&cgu_clk CLK_SYS_SPI_REF>;
clock-names = "spi_clk";
cs-gpio = <&cs_gpio 0>;
num-cs = <1>;
cs-gpios = <&cs_gpio 0>;
spi_flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
......
......@@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
config TARGET_LX2162AQDS
bool "Support lx2162aqds"
select ARCH_LX2162A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
help
Support for NXP LX2162AQDS platform.
The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
......
......@@ -5,11 +5,11 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A008997 if USB
select SYS_FSL_ERRATUM_A009007 if USB
select SYS_FSL_ERRATUM_A009008 if USB
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009798 if USB
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_HAS_CCI400
......
......@@ -115,7 +115,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
!TARGET_LX2160AQDS && \
!TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
......
......@@ -208,6 +208,35 @@ config ARCH_LS2080A
imply DISTRO_DEFAULTS
imply PANIC_HANG
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A050106
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
......@@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106
help
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
to erratum A-009007, but this one is for LX2160A,
to erratum A-009007, but this one is for LX2160A and LX2162A,
and the register value is different.
config SYS_FSL_ERRATUM_A010315
......@@ -362,6 +391,7 @@ config MAX_CPUS
default 16 if ARCH_LS2080A
default 8 if ARCH_LS1088A
default 16 if ARCH_LX2160A
default 16 if ARCH_LX2162A
default 1
help
Set this number to the maximum number of possible CPUs in the SoC.
......@@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV
int "DUART clock divider"
default 1 if ARCH_LS1043A
default 4 if ARCH_LX2160A
default 4 if ARCH_LX2162A
default 2
help
This is the divider that is used to derive DUART clock from Platform
......@@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV
default 4 if ARCH_LS1012A
default 4 if ARCH_LS1028A
default 8 if ARCH_LX2160A
default 8 if ARCH_LX2162A
default 8 if ARCH_LS1088A
default 2
help
......@@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV
default 4 if ARCH_LS1012A
default 4 if ARCH_LS1028A
default 8 if ARCH_LX2160A
default 8 if ARCH_LX2162A
default 8 if ARCH_LS1088A
default 2
help
......@@ -560,14 +593,14 @@ config SYS_FSL_EC1
bool
help
Ethernet controller 1, this is connected to
MAC17 for LX2160A or to MAC3 for other SoCs
MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
Provides DPAA2 capabilities
config SYS_FSL_EC2
bool
help
Ethernet controller 2, this is connected to
MAC18 for LX2160A or to MAC4 for other SoCs
MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
Provides DPAA2 capabilities
config SYS_FSL_ERRATUM_A008336
......
......@@ -27,6 +27,11 @@ obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LX2162A),)
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
obj-y += icid.o ls2088_ids.o
......
......@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
};
#define EARLY_PGTABLE_SIZE 0x5000
......@@ -403,7 +406,7 @@ void cpu_name(char *name)
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
strcpy(name, cpu_type_list[i].name);
#ifdef CONFIG_ARCH_LX2160A
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
if (IS_C_PROCESSOR(svr))
strcat(name, "C");
#endif
......@@ -1229,7 +1232,7 @@ __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(ulong addr)
{
#ifdef CONFIG_ARCH_LX2160A
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
/* clear the RST_REQ_MSK and SW_RST_REQ */
out_le32(rstcr, 0x0);
......
......@@ -9,6 +9,7 @@ SoC overview
7. LS2081A
8. LX2160A
9. LS1028A
10. LX2162A
LS1043A
---------
......@@ -379,3 +380,58 @@ The LS1028A SoC includes the following function and features:
- Layerscape Trust Architecture
- Service Processor (SP) provides pre-boot initialization and secure-boot
capabilities
LX2162A
--------
The QorIQ LX2162A processor is built on the Layerscape architecture
combining sixteen ARM A72 processor cores with advanced, high-performance
datapath acceleration and network, peripheral interfaces required for
networking, wireless infrastructure, storage, and general-purpose embedded
applications.
LX2162A is compliant with the Layerscape Chassis Generation 3.2.
The LX2162A SoC includes the following function and features:
Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
Cache Coherent Interconnect Fabric (CCN508)
One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
Data path acceleration architecture (DPAA2)
12 Serdes lanes at up to 25 GHz
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
Support for XFI (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
Energy efficient Ethernet support (802.3az)
IEEE 1588 support.
High-speed peripheral interfaces
One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
Two PCIe Gen 3.0 4-lane controllers.
Four serial ATA (SATA 3.0) controllers.
One USB 3.0 controllers with integrated PHY
Two Enhanced secure digital host controllers
Two Controller Area Network (CAN) modules
Flexible Serial peripheral interface (FlexSPI) controller.
Three Serial peripheral interface (SPI) controllers.
Eight I2C Controllers.
Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
General Purpose IO (GPIO)
Support for hardware virtualization and partitioning (ARM MMU-500)
Support for GIC (ARM GIC-500)
QorIQ platform Trust Architecture 3.0
One Secure WatchDog timer and one Non-Secure Watchdog timer.
ARM Generic Timer
Two Flextimers
Debug supporting run control, data acquisition, high-speed trace,
performance/event monitoring
Thermal Monitor Unit (TMU) with +/- 2C accuracy
Support for Voltage ID (VID) for yield improvement
LX2162A SoC has 2 more similar SoC personalities
1)LX2122A, few difference w.r.t. LX2162A:
a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
2)LX2082A, few difference w.r.t. LX2162A:
a) Eight 64-bit ARM v8 Cortex-A72 CPUs
......@@ -400,10 +400,12 @@ void fdt_fixup_remove_jr(void *blob)
while (jr_node != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
jr_offset = fdt_read_number(reg, addr_cells);
if (jr_offset == used_jr) {
fdt_del_node(blob, jr_node);
break;
if (reg) {
jr_offset = fdt_read_number(reg, addr_cells);
if (jr_offset == used_jr) {
fdt_del_node(blob, jr_node);
break;
}
}
jr_node = fdt_node_offset_by_compatible(blob, jr_node,
"fsl,sec-v4.0-job-ring");
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016-2018 NXP
* Copyright 2016-2018, 2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
......@@ -26,7 +26,7 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_ARCH_LX2160A
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
int xfi_dpmac[XFI14 + 1];
int sgmii_dpmac[SGMII18 + 1];
int a25gaui_dpmac[_25GE10 + 1];
......@@ -159,7 +159,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
else {
serdes_prtcl_map[lane_prtcl] = 1;
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_ARCH_LX2160A
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
(int)lane_prtcl);
......@@ -552,7 +552,7 @@ void fsl_serdes_init(void)
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
int i , j;
#ifdef CONFIG_ARCH_LX2160A
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
for (i = XFI1, j = 1; i <= XFI14; i++, j++)
xfi_dpmac[i] = j;
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015, Freescale Semiconductor, Inc.
* Copyright 2019 NXP Semiconductors
* Copyright 2019-2020 NXP
*
* Derived from arch/power/cpu/mpc85xx/speed.c
*/
......@@ -180,7 +180,7 @@ int get_clocks(void)
#ifdef CONFIG_FSL_ESDHC
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
clock = sys_info.freq_cga_m2;
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
clock = sys_info.freq_systembus;
#endif
gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2020 NXP
*/
#include <common.h>
......@@ -11,6 +11,22 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
#if defined(CONFIG_ARCH_LX2162A)
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
{0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
{0x03, {XFI6, XFI5, XFI4, XFI3 } },
{0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
{0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
{0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
{0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
{0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
{0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
{0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
{}
};
#else
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
......@@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
{}
};
#endif
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
#include <common.h>
......@@ -33,13 +33,10 @@
#include <fsl_validate.h>
#endif
#include <fsl_immap.h>
#ifdef CONFIG_TFABOOT
#include <env_internal.h>
#endif
#include <dm.h>
#include <dm/device_compat.h>
#include <linux/err.h>
#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
#ifdef CONFIG_GIC_V3_ITS
DECLARE_GLOBAL_DATA_PTR;
#endif
......@@ -186,7 +183,8 @@ static void erratum_a008997(void)
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
defined(CONFIG_ARCH_LX2162A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
......@@ -222,7 +220,7 @@ static void erratum_a009007(void)
#if defined(CONFIG_FSL_LSCH3)
static void erratum_a050106(void)
{
#if defined(CONFIG_ARCH_LX2160A)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
void __iomem *dcsr = (void __iomem *)DCSR_BASE;
PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
......@@ -392,7 +390,8 @@ void fsl_lsch3_early_init_f(void)
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
defined(CONFIG_ARCH_LX2162A)
set_icids();
#endif
}
......@@ -954,28 +953,12 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
* check if gd->env_addr is default_environment; then setenv bootcmd
* and mcinitcmd.
*/
#ifdef CONFIG_SYS_RELOC_GD_ENV_ADDR
if (gd->env_addr == (ulong)&default_environment[0]) {
#else
if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) {
#endif
fsl_setenv_bootcmd();
fsl_setenv_mcinitcmd();
}
/*
* If the boot mode is secure, default environment is not present then
* setenv command needs to be run by default
* Set bootcmd and mcinitcmd if they don't exist in the environment.
*/
#ifdef CONFIG_CHAIN_OF_TRUST
if ((fsl_check_boot_mode_secure() == 1)) {
if (!env_get("bootcmd"))
fsl_setenv_bootcmd();
if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
}
#endif
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
......
......@@ -204,7 +204,6 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
dtb-$(CONFIG_ARCH_MVEBU) += \
armada-3720-db.dtb \
armada-3720-espressobin.dtb \
armada-3720-espressobin-emmc.dtb \
armada-3720-turris-mox.dtb \
armada-3720-uDPU.dtb \
armada-375-db.dtb \
......@@ -415,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
fsl-lx2160a-qds-20-11-x.dtb
fsl-lx2160a-qds-20-11-x.dtb \
fsl-lx2162a-qds.dtb\
fsl-lx2162a-qds-17-x.dtb\
fsl-lx2162a-qds-18-x.dtb\
fsl-lx2162a-qds-20-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
......@@ -643,14 +646,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-aristainetos2b_4.dtb \
imx6dl-aristainetos2b_7.dtb \
imx6dl-aristainetos2b_csl_4.dtb \
imx6dl-aristainetos2b_csl_7.dtb \
imx6dl-aristainetos2c_4.dtb \
imx6dl-aristainetos2c_7.dtb \
imx6dl-aristainetos2c_cslb_7.dtb \
imx6dl-brppt2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
......@@ -768,6 +765,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
imx8qm-rom7720-a1.dtb \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-apalis.dtb \
fsl-imx8qxp-mek.dtb \
imx8-deneb.dtb \
imx8-giedi.dtb
......
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
* Copyright (C) 2018 Marvell
*
* Romain Perier <romain.perier@free-electrons.com>
* Konstantin Porotchkin <kostap@marvell.com>
*
*/
/*
* Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
*/
/dts-v1/;
#include "armada-3720-espressobin.dtsi"
/ {
model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
"marvell,armada3720", "marvell,armada3710";
};
/* U11 */
&sdhci1 {
non-removable;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs400-1_8v;
marvell,xenon-emmc;
marvell,xenon-tun-count = <9>;
marvell,pad-type = "fixed-1-8v";
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;