Commit 8a8d24bd authored by Simon Glass's avatar Simon Glass
Browse files

dm: treewide: Rename ..._platdata variables to just ..._plat



Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
parent b012ff1f
......@@ -18,7 +18,7 @@ struct gpio_bank {
};
/* Information about a GPIO bank */
struct hikey_gpio_platdata {
struct hikey_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
};
......
......@@ -8,7 +8,7 @@
#include <asm/arch/sci/types.h>
struct imx8_power_domain_platdata {
struct imx8_power_domain_plat {
sc_rsrc_t resource_id;
};
......
......@@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
struct imx8m_power_domain_platdata {
struct imx8m_power_domain_plat {
int resource_id;
int has_pd;
struct power_domain pd;
......
......@@ -20,7 +20,7 @@ struct vybrid_gpio_regs {
u32 gpio_pdir;
};
struct vybrid_gpio_platdata {
struct vybrid_gpio_plat {
unsigned int chip;
u32 base;
const char *port_name;
......
......@@ -25,7 +25,7 @@
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
struct omap_gpio_platdata {
struct omap_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;
......
......@@ -6,7 +6,7 @@
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
struct omap_i2c_platdata {
struct omap_i2c_plat {
ulong base; /* address of registers in physical memory */
int speed;
int ip_rev;
......
......@@ -23,7 +23,7 @@ struct omap_musb_board_data {
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
struct ti_musb_platdata {
struct ti_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;
......
......@@ -213,7 +213,7 @@ void at91_sdram_hw_init(void)
}
/* Platform data for the GPIOs */
static const struct at91_port_platdata at91sam9260_plat[] = {
static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
......
......@@ -167,7 +167,7 @@ void at91_mci_hw_init(void)
#endif
/* Platform data for the GPIOs */
static const struct at91_port_platdata at91sam9260_plat[] = {
static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },
......
......@@ -7,7 +7,7 @@
#define _ATMEL_SERIAL_H
/* Information about a serial port */
struct atmel_serial_platdata {
struct atmel_serial_plat {
uint32_t base_addr;
};
......
......@@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio)
}
/* Platform data for each GPIO port */
struct at91_port_platdata {
struct at91_port_plat {
uint32_t base_addr;
const char *bank_name;
};
......
......@@ -52,11 +52,11 @@ struct bcm2835_gpio_regs {
};
/**
* struct bcm2835_gpio_platdata - GPIO platform description
* struct bcm2835_gpio_plat - GPIO platform description
*
* @base: Base address of GPIO controller
*/
struct bcm2835_gpio_platdata {
struct bcm2835_gpio_plat {
unsigned long base;
};
......
......@@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata lpc32xx_uart[] = {
static const struct ns16550_plat lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
......@@ -55,7 +55,7 @@ static const struct ns16550_platdata lpc32xx_uart[] = {
};
#if defined(CONFIG_LPC32XX_HSUART)
static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
{ HS_UART1_BASE, },
{ HS_UART2_BASE, },
{ HS_UART7_BASE, },
......
......@@ -212,7 +212,7 @@ struct dp_hdmi_dev {
};
/* platform data for the driver model */
struct nx_display_platdata {
struct nx_display_plat {
int module;
struct dp_sync_info sync;
struct dp_ctrl_info ctrl;
......@@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps);
#if defined CONFIG_SPL_BUILD || \
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
int nx_display_probe(struct nx_display_platdata *plat);
int nx_display_probe(struct nx_display_plat *plat);
#endif
#endif
......@@ -80,7 +80,7 @@ int dram_init_banksize(void)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata am33xx_serial[] = {
static const struct ns16550_plat am33xx_serial[] = {
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM2
......@@ -113,7 +113,7 @@ U_BOOT_DEVICES(am33xx_uarts) = {
};
#ifdef CONFIG_DM_I2C
static const struct omap_i2c_platdata am33xx_i2c[] = {
static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
......@@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
static const struct omap_gpio_platdata am33xx_gpio[] = {
static const struct omap_gpio_plat am33xx_gpio[] = {
{ 0, AM33XX_GPIO0_BASE },
{ 1, AM33XX_GPIO1_BASE },
{ 2, AM33XX_GPIO2_BASE },
......@@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = {
};
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
static struct ti_musb_platdata usb0 = {
static struct ti_musb_plat usb0 = {
.base = (void *)USB0_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
.plat = {
......@@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = {
},
};
static struct ti_musb_platdata usb1 = {
static struct ti_musb_plat usb1 = {
.base = (void *)USB1_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
.plat = {
......
......@@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void);
#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
static const struct omap_gpio_plat omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ 2, OMAP34XX_GPIO3_BASE },
......
......@@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int px30_syscon_bind_of_platdata(struct udevice *dev)
static int px30_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
......@@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = {
.name = "rockchip_px30_pmu",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
.name = "rockchip_px30_pmugrf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 1,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_grf) = {
.name = "rockchip_px30_grf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 2,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
#endif
......@@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
static int rk3188_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
......@@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = {
.name = "rockchip_rk3188_noc",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_grf) = {
.name = "rockchip_rk3188_grf",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 1,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
.name = "rockchip_rk3188_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 2,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
#endif
......@@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
......@@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = {
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
.name = "rockchip_rk3288_grf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 1,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
.name = "rockchip_rk3288_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 2,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
.name = "rockchip_rk3288_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 3,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
#endif
......@@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
static int rk3368_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
......@@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = {
.name = "rockchip_rk3368_grf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
.name = "rockchip_rk3368_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 1,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.name = "rockchip_rk3368_msch",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 2,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
.name = "rockchip_rk3368_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 3,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
#endif
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