Commit 9d082687 authored by Jelle van der Waa's avatar Jelle van der Waa Committed by Heiko Schocher
Browse files

sunxi: Add support for the I2C controller which is part of the PRCM


Signed-off-by: default avatarJelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>

applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs
Signed-off-by: Heiko Schocher's avatarHeiko Schocher <hs@denx.de>
parent 904dfbfd
......@@ -77,6 +77,16 @@ int clock_twi_onoff(int port, int state)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (port == 5) {
if (state)
prcm_apb0_enable(
PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
else
prcm_apb0_disable(
PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_I2C);
return 0;
}
/* set the apb clock gate for twi */
if (state)
setbits_le32(&ccm->apb2_gate,
......
......@@ -33,3 +33,15 @@ void prcm_apb0_enable(u32 flags)
/* deassert reset for module */
setbits_le32(&prcm->apb0_reset, flags);
}
void prcm_apb0_disable(u32 flags)
{
struct sunxi_prcm_reg *prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
/* assert reset for module */
clrbits_le32(&prcm->apb0_reset, flags);
/* close the clock for module */
clrbits_le32(&prcm->apb0_gate, flags);
}
......@@ -134,6 +134,7 @@
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_TWI_BASE 0x01f02400
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
......
......@@ -199,6 +199,8 @@ enum sunxi_gpio_number {
#define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL_R_RSB 2
#define SUN8I_H3_GPL_R_TWI 2
#define SUN8I_A23_GPL_R_TWI 3
#define SUN8I_GPL_R_UART 2
#define SUN9I_GPN_R_RSB 3
......
......@@ -23,6 +23,9 @@
#ifdef CONFIG_I2C4_ENABLE
#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE
#endif
#ifdef CONFIG_R_I2C_ENABLE
#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
#define CONFIG_SYS_TCLK 24000000
......
......@@ -236,5 +236,7 @@ struct sunxi_prcm_reg {
};
void prcm_apb0_enable(u32 flags);
void prcm_apb0_disable(u32 flags);
#endif /* __ASSEMBLY__ */
#endif /* _PRCM_H */
......@@ -363,6 +363,12 @@ config I2C3_ENABLE
See I2C0_ENABLE help text.
endif
config R_I2C_ENABLE
bool "Enable the PRCM I2C/TWI controller"
default n
---help---
Set this to y to enable the I2C controller which is part of the PRCM.
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
......
......@@ -422,6 +422,12 @@ void i2c_init_board(void)
clock_twi_onoff(4, 1);
#endif
#endif
#ifdef CONFIG_R_I2C_ENABLE
clock_twi_onoff(5, 1);
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
#endif
}
#ifdef CONFIG_SPL_BUILD
......
......@@ -12,3 +12,4 @@ CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_FPGA is not set
CONFIG_CMD_GPIO=y
CONFIG_R_I2C_ENABLE=y
......@@ -127,6 +127,10 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
#ifdef CONFIG_I2C_MVTWSI_BASE4
case 4:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE5
case 5:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5;
#endif
default:
printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
......@@ -487,3 +491,10 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE5
U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
twsi_i2c_read, twsi_i2c_write,
twsi_i2c_set_bus_speed,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
#endif
......@@ -212,7 +212,7 @@
#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
defined CONFIG_I2C4_ENABLE
defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_I2C_SPEED 400000
......
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