Commit b51d103c authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

- SoCFPGA DT and reset cleanup, AE MCVEVK board support.
parents 9a32caf5 9e6ed1a3
......@@ -296,6 +296,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
......
// SPDX-License-Identifier: GPL-2.0+ OR X11
/ {
chosen {
u-boot,dm-pre-reloc;
};
clocks {
u-boot,dm-pre-reloc;
altera_arria10_hps_eosc1 {
u-boot,dm-pre-reloc;
};
altera_arria10_hps_cb_intosc_ls {
u-boot,dm-pre-reloc;
};
altera_arria10_hps_f2h_free {
u-boot,dm-pre-reloc;
};
};
clock_manager@0xffd04000 {
u-boot,dm-pre-reloc;
mainpll {
u-boot,dm-pre-reloc;
};
perpll {
u-boot,dm-pre-reloc;
};
alteragrp {
u-boot,dm-pre-reloc;
};
};
pinmux@0xffd07000 {
u-boot,dm-pre-reloc;
shared {
u-boot,dm-pre-reloc;
};
dedicated {
u-boot,dm-pre-reloc;
};
dedicated_cfg {
u-boot,dm-pre-reloc;
};
fpga {
u-boot,dm-pre-reloc;
};
};
noc@0xffd10000 {
u-boot,dm-pre-reloc;
firewall {
u-boot,dm-pre-reloc;
};
};
fpgabridge@0 {
u-boot,dm-pre-reloc;
};
fpgabridge@1 {
u-boot,dm-pre-reloc;
};
fpgabridge@2 {
u-boot,dm-pre-reloc;
};
fpgabridge@3 {
u-boot,dm-pre-reloc;
};
fpgabridge@4 {
u-boot,dm-pre-reloc;
};
fpgabridge@5 {
u-boot,dm-pre-reloc;
};
};
......@@ -14,7 +14,8 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
#include "socfpga_arria10.dtsi"
/ {
model = "Altera SOCFPGA Arria 10";
......
......@@ -17,6 +17,8 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
#include "socfpga_arria10_handoff_u-boot.dtsi"
/ {
chosen {
......
......@@ -11,8 +11,6 @@
*</auto-generated>
*/
#include "socfpga_arria10.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
......@@ -24,13 +22,11 @@
/* Clock sources */
clocks {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
/* Clock source: altera_arria10_hps_eosc1 */
altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
......@@ -39,7 +35,6 @@
/* Clock source: altera_arria10_hps_cb_intosc_ls */
altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
......@@ -48,7 +43,6 @@
/* Clock source: altera_arria10_hps_f2h_free */
altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
......@@ -62,14 +56,12 @@
* Binding: device
*/
i_clk_mgr: clock_manager@0xffd04000 {
u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-clk-init";
reg = <0xffd04000 0x00000200>;
reg-names = "soc_clock_manager_OCP_SLV";
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
mainpll {
u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <191>; /* Field: vco1.numer */
......@@ -98,7 +90,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
perpll {
u-boot,dm-pre-reloc;
vco0-psrc = <0>; /* Field: vco0.psrc */
vco1-denom = <1>; /* Field: vco1.denom */
vco1-numer = <159>; /* Field: vco1.numer */
......@@ -124,7 +115,6 @@
/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
alteragrp {
u-boot,dm-pre-reloc;
nocclk = <0x0384000b>; /* Register: nocclk */
mpuclk = <0x03840001>; /* Register: mpuclk */
};
......@@ -136,7 +126,6 @@
* Binding: pinmux
*/
i_io48_pin_mux: pinmux@0xffd07000 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "pinctrl-single";
......@@ -145,7 +134,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
shared {
u-boot,dm-pre-reloc;
reg = <0xffd07000 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
......@@ -202,7 +190,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated {
u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x0000000f>;
......@@ -225,7 +212,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
dedicated_cfg {
u-boot,dm-pre-reloc;
reg = <0xffd07200 0x00000200>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x003f3f3f>;
......@@ -252,7 +238,6 @@
/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
fpga {
u-boot,dm-pre-reloc;
reg = <0xffd07400 0x00000100>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x00000001>;
......@@ -283,13 +268,11 @@
* Binding: device
*/
i_noc: noc@0xffd10000 {
u-boot,dm-pre-reloc;
compatible = "altr,socfpga-a10-noc";
reg = <0xffd10000 0x00008000>;
reg-names = "mpu_m0";
firewall {
u-boot,dm-pre-reloc;
/*
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*/
#include "socfpga_cyclone5.dtsi"
/ {
model = "Aries/DENX MCV";
compatible = "altr,socfpga-cyclone5", "altr,socfpga";
memory@0 {
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1 GiB */
};
};
&mmc0 { /* On-SoM eMMC */
bus-width = <8>;
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
* Copyright (C) 2019 Wolfgang Grandegger <wg@aries-embedded.de>
*/
#include "socfpga-common-u-boot.dtsi"
&watchdog0 {
status = "disabled";
};
&mmc {
u-boot,dm-pre-reloc;
};
&uart0 {
clock-frequency = <100000000>;
u-boot,dm-pre-reloc;
};
&porta {
bank-name = "porta";
};
&portb {
bank-name = "portb";
};
&portc {
bank-name = "portc";
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*/
#include "socfpga_cyclone5_mcv.dtsi"
/ {
model = "Aries/DENX MCV EVK";
compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
aliases {
ethernet0 = &gmac0;
stmpe-i2c0 = &stmpe1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&gmac0 {
phy-mode = "rgmii";
status = "okay";
};
&gpio0 { /* GPIO 0 ... 28 */
status = "okay";
};
&gpio1 { /* GPIO 29 ... 57 */
status = "okay";
};
&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
stmpe1: stmpe811@41 {
compatible = "st,stmpe811";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
id = <0>;
blocks = <0x5>;
irq-gpio = <&portb 28 0x4>; /* GPIO 57, trig. level HI */
stmpe_touchscreen {
compatible = "st,stmpe-ts";
ts,sample-time = <4>;
ts,mod-12b = <1>;
ts,ref-sel = <0>;
ts,adc-freq = <1>;
ts,ave-ctrl = <1>;
ts,touch-det-delay = <3>;
ts,settling = <4>;
ts,fraction-z = <7>;
ts,i-drive = <1>;
};
};
};
&uart0 {
status = "okay";
};
&usb1 {
status = "okay";
};
......@@ -64,6 +64,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
......@@ -128,6 +132,7 @@ config SYS_BOARD
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
......@@ -139,6 +144,7 @@ config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
......@@ -159,6 +165,7 @@ config SYS_CONFIG_NAME
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
......
......@@ -8,7 +8,6 @@
#include <dt-bindings/reset/altr,rst-mgr.h>
void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
......
......@@ -8,7 +8,6 @@
#define _RESET_MANAGER_S10_
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void socfpga_bridges_reset(int enable);
......
......@@ -61,14 +61,6 @@ void socfpga_per_reset_all(void)
writel(0xffffffff, &reset_manager_base->per2_mod_reset);
}
/*
* Release peripherals from reset based on handoff
*/
void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
#define L3REGS_REMAP_OCRAM_MASK 0x01
......
......@@ -94,17 +94,6 @@ void socfpga_bridges_reset(int enable)
}
}
/*
* Release peripherals from reset based on handoff
*/
void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per1modrst);
/* Enable OCP first */
writel(~RSTMGR_PER0MODRST_OCP_MASK, &reset_manager_base->per0modrst);
writel(0, &reset_manager_base->per0modrst);
}
/*
* Return non-zero if the CPU has been warm reset
*/
......
......@@ -175,8 +175,7 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
sysmgr_config_warmrstcfgio(0);
/* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
/* Set bridges handoff value */
socfpga_bridges_set_handoff_regs(true, true, true);
debug("Unfreezing/Thaw all I/O banks\n");
......
Aries MCVEVK BOARD
M: Wolfgang Grandegger <wg@aries-embedded.de>
S: Maintained
F: board/aries/mcvevk/
F: include/configs/socfpga_mcvevk.h
F: configs/socfpga_mcvevk_defconfig
F: arch/arm/dts/socfpga_cyclone5_mcv.dtsi
F: arch/arm/dts/socfpga_cyclone5_mcvevk.dts
F: arch/arm/dts/socfpga_cyclone5_mcvevk-u-boot.dtsi
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
obj-y := socfpga.o
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Altera SoCFPGA IOCSR configuration
*/
#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = {
0x00000000,
0x00000000,
0x0FF00000,
0xC0000000,
0x0000003F,
0x00008000,
0x00000000,
0x18060000,
0x00000060,
0x00000000,
0x00000000,
0x00004000,
0x0C0300C0,
0x00000000,
0x0C000000,
0x0000C030,
0x0000C030,
0x00002000,
0x06018060,
0x06018000,
0x06000018,
0x00006018,
0x01806018,
0x00001000,
};
const unsigned long iocsr_scan_chain1_table[] = {
0x000C0300,
0x300C0000,
0x300000C0,
0x000000C0,
0x000300C0,
0x00008000,
0x00060180,
0x18060000,
0x18000000,
0x00000060,
0x00018060,
0x00004000,
0x000300C0,
0x0C030000,
0x0C000000,
0x00000030,
0x0000C030,
0x00002000,
0x00018060,
0x06018000,
0x01FE0000,
0xF8000000,
0x00000007,
0x00001000,
0x0300C030,
0x00000000,
0x03000000,
0x0000000C,
0x00000000,
0x00000800,
0x00006018,
0x01806000,
0x00000000,
0x00000000,
0x00001806,
0x00000400,
0x0000300C,
0x00C03000,
0x00C00000,
0x00000003,
0x00000C03,
0x00000200,
0x00001806,
0x00601800,
0x80600000,
0x80000001,
0x00000601,
0x00000100,
0x00001000,
0x00300C00,
0xC0300000,
0xC0000000,
0x00000300,
0x00000080,
};
const unsigned long iocsr_scan_chain2_table[] = {
0x300C0300,
0x00000000,
0x0FF00000,
0x00000000,
0x0C0300C0,
0x00008000,
0x00060180,
0x00000000,
0x18000000,
0x00018060,
0x06018060,
0x00004000,
0x200300C0,
0x0C030000,
0x0C000000,
0x00000030,
0x0000C030,
0x00002000,
0x00018060,
0x00000000,
0x06000000,
0x00010018,
0x01806018,
0x00001000,