Commit f60c6fbb authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu Committed by Michal Simek
Browse files

ARM: zynq: slcr: Dont modify the reserved bits



Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: default avatarNathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent 3ad87ca1
......@@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment