Commit f60c6fbb authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu Committed by Michal Simek
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ARM: zynq: slcr: Dont modify the reserved bits

Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <>
Reviewed-by: default avatarPeter Crosthwaite <>
Reviewed-by: default avatarNathan Rossi <>
Signed-off-by: default avatarMichal Simek <>
parent 3ad87ca1
......@@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);
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