- 04 Sep, 2019 24 commits
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This patch adds a check to udp_len to fix unbounded memcpy for CVE-2019-14192, CVE-2019-14193 and CVE-2019-14199. Signed-off-by:
Cheng Liu <liucheng32@huawei.com> Reviewed-by:
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reported-by:
Fermín Serna <fermin@semmle.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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The net_random_ethaddr() tries to get some entropy from different startup times of a board. The seed is initialized with get_timer() which has only a granularity of milliseconds. We can do better if we use get_ticks() which returns the raw timer ticks. Using this we have a higher chance of getting different values at startup. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
Acked-by: -
With commit c6d07bf4 ("net/macb: increase RX buffer size for GEM") ethernet support does not work any more with d-cache enabled on the AT91SAM. The reason is, that MACB_RX_BUFFER_SIZE was changed from 4096 to 128 but this change was not refected in the rx_buffer flush and invalidate functions, as these also use this macro. This patch now fixes this by calculating the rx buffer size correctly again in those functions. With this change, ethernet works again reliably on my AT91SAM board. Signed-off-by:
Stefan Roese <sr@denx.de> Fixes: c6d07bf4 ("net/macb: increase RX buffer size for GEM") Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: -
The same compatible = "altr,socfpga-stmmac" appears in both drivers/net/designware.c and drivers/net/dwmac_socfgpa.c, creating ambiguity in which driver will be bound. For Intel/Altera SoC devices, dwmac_socfpga.c is the correct driver. So drop the compatible string from designware.c. Signed-off-by:
Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by:
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This reverts commit 1b0c9914. Commit 1b0c9914 ("net: macb: Fixed reading MII_LPA register") causes 100Mbps does not work any more with SiFive FU540 GEM on the HiFive Unleashed board. Revert it. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Acked-by: -
The driver model has been supported for network drivers since 2015. It is time to convert the remaining boards. Set July 2020 as a timeline. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Simon Glass <sjg@chromium.org> Acked-by:
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It was missing in the original submission and not having it in place causes issues with probing of PCI devices. Signed-off-by:
Alex Marginean <alexm.osslist@gmail.com> Acked-by:
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Align the board and driver prototype for board_interface_eth_init to avoid execution issue (the interface_type parameter is defined as int or phy_interface_t). To have a generic weak function (it should be reused by other driver) I change the prototype to use directly udevice. This prototype is added in netdev.h to allow compilation check and avoid warning when compiling with W=1 on file board/st/stm32mp1/stm32mp1.c warning: no previous prototype for 'board_interface_eth_init'\ [-Wmissing-prototypes] int board_interface_eth_init(int interface_type, .... ^~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by:Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: -
This patch solves many warnings when compiling with W=1: warning: no previous prototype for '....' [-Wmissing-prototypes] Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com> Acked-by:
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Do not use random value from stack as return value of pfe_phy_write(). Indicated by cppcheck. Signed-off-by:
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SANDBOX_PHY_REG_CNT is not an allowable index for the array u16 reg[SANDBOX_PHY_REG_CNT]. Identified by cppcheck. Fixes: b47edf80 ("test: dm_mdio: add a 2nd register to the emulated PHY") Signed-off-by:
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mvpp2 already has support for setting MAC addresses but this functionality was not exposed to the ethernet core. This commit exposes this functionality so that MAC address assignments stored in U-Boot's environment are correctly applied before Linux boots. Signed-off-by:
Matt Pelland <mpelland@starry.com> Acked-by:
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Implicitly Marvell MDIO driver uses DT node names for devices, but in this case that is not unique. Set MDIO device names for master/slave to cpm/cps. Signed-off-by:
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This patch adds a separate driver for the MDIO interface of the Marvell Ethernet controllers based on driver model. There are two reasons to have a separate driver rather than including it inside the MAC driver itself: *) The MDIO interface is shared by all Ethernet ports, so a driver must guarantee non-concurrent accesses to this MDIO interface. The most logical way is to have a separate driver that handles this single MDIO interface, used by all Ethernet ports. *) The MDIO interface is the same between the existing mv643xx_eth driver and the new mvneta/mvpp2 driver. Even though it is for now only used by the mvneta/mvpp2 driver, it will in the future be used by the mv643xx_eth driver as well. This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE 802.3 Clause 45. This patch also adds device tree binding for marvell MDIO driver. Signed-off-by:Ken Ma <make@marvell.com> Signed-off-by:
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Adds a binding document for mdio. A notable deviation from corresponding Linux binding is the introduction of device-name optional property, which can be used to name MDIO buses. Two reset optional properties described by Linux binding are also not present as they don't seem to be used in U-Boot at this time. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> -
Use the optional property device-name to name the MDIO bus. This works around limitations with using the DT node name on devices such as Armada-8040, which integrates two cp100 cores, both featuring MDIOs at the same relative offsets and with the same DT node names. The concept was originally proposed by Marvell as a custom property called mdio-name specific to Marvell driver. This patch uses the more generic property device-name and moves this into MDIO class code so other can use it as well. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Enable CONFIG_CMD_PCAP for testing PCAP capture. Signed-off-by:
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Add documentation for new "pcap" command. Signed-off-by:
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Add support for capturing ethernet packets and storing them in memory in PCAP(2.4) format, later to be analyzed by any PCAP viewer software (IE. Wireshark) This feature greatly assist debugging network issues such as detecting dropped packets, packet corruption etc. Signed-off-by:
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Create drivers/net/fsl-mc/Kconfig and move fsl-mc specific configs from arch/arm/cpu/armv8/fsl-layerscape/Kconfig to this new Kconfig Signed-off-by:
Florinel Iordache <florinel.iordache@nxp.com> Acked-by:
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This driver is used for MDIO muxes driven over I2C. This is currently used on Freescale LS1028A QDS board, on which the physical MDIO MUX is controlled by an on-board FPGA which in turn is configured through I2C. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Joe Hershberger authored
This reverts commit d9a9174f.
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Joe Hershberger authored
Document that the lack of breaks is intentional. Series-to: u-boot Series-cc: ti Signed-off-by: -
Joe Hershberger authored
Don't allow unterminated strings Signed-off-by:
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- 03 Sep, 2019 16 commits
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https://gitlab.denx.de/u-boot/custodians/u-boot-arcTom Rini authored
These are some very late changes mostly required to get 64-bit division working on ARC boards. For that we had to import missing parts of libgcc and add compiler flags to EMSDP which otherwise used very simple profile for compliation. And while at it another fix for EM SDP initialization is inluded as well.
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Alexey Brodkin authored
Even though EM SDP is FPGA-based board and different FPGA images (known as .bit-files) are awailable for the board still there's a common subset of options we may rely on for all configs. These are: * Normalizer * Swap instructions * Simple multiplier * Barrel-shifter * Floating-point unit * Shorter instructions (code density) This among other improvements allows to compile code with 64-bit divisions, see [1]. [1] https://patchwork.ozlabs.org/patch/1156541/ Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Kever Yang <kever.yang@rock-chips.com>
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Alexey Brodkin authored
As reported by Kever here [1] we were unable to compile 64-bit division code due to missing definition of __udivdi3(). Import its implementation and __udivmoddi4() as its direct dependency from today's libgcc [2]. [1] https://patchwork.ozlabs.org/patch/1146845/ [2] https://github.com/gcc-mirror/gcc/commit/5d8723600bc0eed41226b5a6785bc02a053b45d5 Signed-off-by:
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Alexey Brodkin authored
If the "Page Mode" is not enabled on the device, read operations from PSRAM may result in incorrect data. Signed-off-by: -
https://gitlab.denx.de/u-boot/custodians/u-boot-i2cTom Rini authored
i2c bugfixes for 2019.10 take 2 - i2c: mxc: add CONFIG_CLK support If CONFIG_CLK is enabled use clk framework for clock settings.
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https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini authored
- Skip unavailable hart in the get_count(). - fu540 set serial env from otp. - fu540 add mmc0 as a boot target device. - Update fix_rela_dyn and add absolute reloc addend. - Andestech PLIC driver will skip unavailable hart. - Support Andestech V5L2 cache driver.
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Rick Chen authored
Use CCTL command to do d-cache write back and invalidate instead of fence. Signed-off-by:
Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
When L2 node exists inside cpus node, uclass_get_device can not parse L2 node successfully. So move it outside from cpus node. Also add tag-ram-ctl and data-ram-ctl attributes for v5l2 cache controller driver. This can adjust timing by requirement from dtb to improve performance. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Add cache enable and disable ops for test coverage. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Add cache enable/disable ops to the DM cache uclass driver Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Rick Chen authored
Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe marked as unavailable, but the cpu node exists indeed. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Marcus Comstedt authored
The addend is now added for RELOC_TYPE relocs. Also, changed the loop structure so that all the R_RISCV_RELATIVE relocs are not required to be at the beginning of the list. Signed-off-by:Marcus Comstedt <marcus@mc.pp.se> Cc: Rick Chen <rick@andestech.com>
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