MMC driver for Meson GX does not initialize DDR config flag
The MMC driver for Meson SOCs does not support DDR transfer modes and does not currently initialize the DDR bit in the MESON_SD_EMMC_CFG register. It simply assumes this bit will be zero. This assumption can fail when a mainline u-boot is chain loaded from a vendor u-boot. (This practice is common when running mainline Linux on Android TV boxes)
This happens on the MyGica ATV495X Android TV box where the vendor u-boot selects a DDR transfer rate for the EMMC. When mainline u-boot is loaded using the vendor u-boot the SOC's DDR bit is still set, but mainline u-boot is trying to use the LEGACY (non DDR) transfer mode. This causes EMMC identification to fail (reading incorrect EXT_CSD data). Data transfers also fail.
The attached patch fixes this problem by explicitly clearing the DDR configuration bit during meson_mmc_probe().