• Archit Taneja's avatar
    OMAP2PLUS: DSS2: DSI: Generalize DSI PLL Clock Naming · 1bb47835
    Archit Taneja authored
    DSI PLL output clock names have been made more generic. The clock name
    describes what the source of the clock and what clock is used for. Some of
    DSI PLL parameters like dividers and DSI PLL source have also been made more
    dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
    and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
    regm_dispc and regm_dsi instead of regm3 and regm4.
    Functions and macros named on the basis of these clock names have also been
    made generic.
    Signed-off-by: default avatarArchit Taneja <archit@ti.com>
    Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>