• Jeremy Fitzhardinge's avatar
    x86/i386: Make sure stack-protector segment base is cache aligned · 1ea0d14e
    Jeremy Fitzhardinge authored
    The Intel Optimization Reference Guide says:
    	In Intel Atom microarchitecture, the address generation unit
    	assumes that the segment base will be 0 by default. Non-zero
    	segment base will cause load and store operations to experience
    	a delay.
    		- If the segment base isn't aligned to a cache line
    		  boundary, the max throughput of memory operations is
    		  reduced to one [e]very 9 cycles.
    	Assembly/Compiler Coding Rule 15. (H impact, ML generality)
    	For Intel Atom processors, use segments with base set to 0
    	whenever possible; avoid non-zero segment base address that is
    	not aligned to cache line boundary at all cost.
    We can't avoid having a non-zero base for the stack-protector
    segment, but we can make it cache-aligned.
    Signed-off-by: default avatarJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
    Cc: <stable@kernel.org>
    LKML-Reference: <4AA01893.6000507@goop.org>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>