• Andi Kleen's avatar
    x86: introduce rdtsc_barrier() · fde1b3fa
    Andi Kleen authored
    
    
    rdtsc_barrier() is a new barrier primitive that stops RDTSC speculation
    to avoid races with timer interrupts on other CPUs.
    
    It expands either to LFENCE (for Intel CPUs) or MFENCE (for
    AMD CPUs) which stops RDTSC on all currently known microarchitectures
    that implement SSE. On CPUs without SSE there is generally no RDTSC
    speculation.
    
    [ mingo@elte.hu: renamed it to rdtsc_barrier() and made it x86-only ]
    Signed-off-by: default avatarAndi Kleen <ak@suse.de>
    Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
    Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    fde1b3fa