- Mar 07, 2022
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T Karthik Reddy authored
slg7xl45106 is i2c based 8-bit gpo expander, gpo pins are set and get by writing and reading corresponding gpo bit value into its data register. Signed-off-by:
T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Reviewed-by:
Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/839f475cc75c97ffb3496a4caa93de2faabdbca2.1645629688.git.michal.simek@xilinx.com
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Ashok Reddy Soma authored
Card detect state stable issue is observed on few ZynqMP boards(SOM), so enable the workaround 'commit b6f44082 ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' for ZynqMP platforms also. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by:
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Ashok Reddy Soma authored
The timeout used in 'commit b6f44082 ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' workaround is 1000ms at a granularity of 1msec. Change it to 1usec, to not waste time incase the cd is stable. Signed-off-by:
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Ashok Reddy Soma authored
In the workaround added with 'commit b6f44082 ("mmc: zynq_sdhci: Wait till sd card detect state is stable")' the timeout variable has post decrement. Whenever timeout happens, this post decrement is making timeout=0xffffffff, so timeout error print and return statement are never reached. Fix it by decrementing it inside the while loop. Signed-off-by:
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Michael Walle authored
Recently, a driver for the ARM Primecell PL35x static memory controller (including NAND controller) was added in linux. Add the corresponding device tree node. Also update cfi-flash registers and location in DT. Signed-off-by:
Michael Walle <michael@walle.cc> Signed-off-by:
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by:
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Michal Simek authored
New binding changed node name from flash@e1000000 to nand-controller@0,0 which should be reflected in the driver. Both names are supported for backward compatibility. Signed-off-by:
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Ashok Reddy Soma authored
Based on discussion at https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got recommendation to use explicit values for all enums. So, add explicit values to all pinctrl related enums for readability. Signed-off-by:
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T Karthik Reddy authored
This reverts commit dfbe492e. Analog bus control register should be programmed in SPL only. This commit 3414712b ("arm64: zynqmp: Writing correct value to ANALOG_BUS") is programming the same. So revert this commit. Signed-off-by:
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Ashok Reddy Soma authored
Add support to read MAC addresses from mac address multirecord. Check if multi record is found, then jump to mac address multirecord by comparing the record type field. If it matches mac address multirecord(0xD2), then copy mac addresses. Copy these read MAC address in xilinx_read_eeprom_fru so that they are updated to eth*addr in board_late_init_xilinx(). Signed-off-by:
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Ashok Reddy Soma authored
In board_late_init_xilinx() eth*addr are updated from the values read from eeprom. Ideally the MAC addresses are updated sequencially. So if any MAC address is invalid, it means there are no further valid values. So optimise this logic by replacing continue with break. Signed-off-by:
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Ashok Reddy Soma authored
fru_checksum function is simply adding all the bytes and returning the sum. If the data passed to this function is all zero's then it will return 0, and the functions calling this api will assume that checksum is correct. Ideally this is not good. Fix this by returning error if all the data is 0's. Signed-off-by:
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Ashok Reddy Soma authored
Fill fru table with 0's before using it, to avoid junk data. Signed-off-by:
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- Mar 06, 2022
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https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini authored
- Fix ARMv5/F1C100 FEL booting - Fix F1C100 reset - Introduce proper F1C100 boot method detection - Enable SPI booting for F1C100 Boot tested from FEL, SPI, SD card and eMMC (where applicable) on Pine64-LTS, Pine-H64, BananaPi M1, OrangePi Zero, LicheePi Nano(F1C100).
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- Mar 05, 2022
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Tom Rini authored
- mailmap file updates, OpenSSL code cleanup, assorted TI platform fixes, typo fix.
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- Mar 04, 2022
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Since OpenSSL 1.1.0, EVP_MD_CTX_create() is EVP_MD_CTX_new() EVP_MD_CTX_destroy() is EVP_MD_CTX_free() EVP_MD_CTX_init() is EVP_MD_CTX_reset() As there's no need to reset a newly created EVP_MD_CTX, moreover EVP_DigestSignInit() does the reset, thus call to EVP_MD_CTX_init() can be dropped. As there's no need to reset an EVP_MD_CTX before it's destroyed, as it will be reset by EVP_MD_CTX_free(), call to EVP_MD_CTX_reset() is not needed and can be dropped. Signed-off-by:Yann Droneaud <ydroneaud@opteya.com>
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Based on looking at top contributors it was seen that top statistics from top contributors don't include all contributions from different email addresses. That's why I checked all top contributors are checked it. git shortlog -n $START..$END -e -s The patch is adding mapping for Bin Meng, Marek Vasut, Masahiro Yamada, Michal Simek, Tom Rini, Wolfgang Denk. And also use mapping for Stefan Roese and Wolfgang Denk to be properly counted. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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If parameter -F is given but FIT support is missing, a NULL pointer might dereferenced (Coverity CID 350249). If incorrect parameters are given, provide a message and show usage. Signed-off-by:Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Fixed misspelled 'disable' in help text. Signed-off-by:Sébastien Szymanski <sebastien.szymanski@armadeus.com>
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Recent unrelated fixes (9876ae7d) revealed that we were missing bits from 2af181b5 in the IOT2050 dt. Add them, but only for main U-Boot. SPL loads from QSPI only, thus cannot use DMA. Signed-off-by:
Jan Kiszka <jan.kiszka@siemens.com>
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Enable config for setting mmc speed mode from U-Boot command line. Signed-off-by:Aswath Govindraju <a-govindraju@ti.com>
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We only want to call do_board_detect() if CONFIG_TI_I2C_BOARD_DETECT is set. Same as done for am64. This makes it possible to add a custom am65 based board design to U-Boot that does not use this board detection mechanism. Signed-off-by:Christian Gmeiner <christian.gmeiner@gmail.com>
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Currently, any u-boot bootloader for ti armv7 platforms using DEFAULT_FIT_TI_ARGS to boot with a fitimage (boot_fit = 1) doesn't boot when built with Yocto Poky (openembedded-core). ## Loading kernel from FIT Image at 90000000 ... Could not find configuration node ERROR: can't get kernel image! Arago forked the kernel-fitimage class [1] and altered the configuration nodes naming while adding the OPTEE support by using FITIMAGE_CONF_BY_NAME by default [2]. The "upstream" kernel-fitimage class from openembedded-core still add the "conf-" prefix for each configuration nodes [3]. The ITS file format (from doc/uImage.FIT/source_file_format.txt) is not really accurate with the expected naming of these nodes. But in practice the "conf-" prefix is widely used. When the FIT image support has been added for ti armv7 platforms the naming from Arago has been used [3]. Fix this issue by adding the prefix expected by the ITS file generated by kernel-fitimage class from openembedded-core. [1] http://arago-project.org/git/meta-arago.git?p=meta-arago.git;a=commitdiff;h=719ab1b2098bcdc59c249e3529fa82cb1b9130e6 [2] http://arago-project.org/git/meta-arago.git?p=meta-arago.git;a=commitdiff;h=f23f2876a0cda89241d031bb7ba0b4256ed90035 [3] https://git.openembedded.org/openembedded-core/tree/meta/classes/kernel-fitimage.bbclass?h=yocto-3.1.13#n290 [3] 1e93cc84 Signed-off-by:
Romain Naour <romain.naour@smile.fr> Cc: Tom Rini <trini@konsulko.com> Reviewed-by:
Denys Dmytriyenko <denys@konsulko.com>
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https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini authored
- pci_mvebu: Minor cleanup (Pali) - mvebu: turris_omnia: Enable ext4 write support (Marek) - a37xx: Misc fixes in PCI and pinctrl (Pali & Marek) - a38x/rtc: Fix null pointer access (Francios) - mvebu: x530: clearfog: Fix ODT configuration (Chris) - kwboot: Fix boot and terminal mode (Pali)
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Public documents about BootROM of some Marvell SoCs are available in the public Web Archive. Put this information into source code. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
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Testes proved that current kwboot version supports also Avanta SoCs. It looks like that Avanta SoCs are using same kwbimage format as Armada. Signed-off-by:
Tony Dinh <mibodhi@gmail.com> Reviewed-by:
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Document -D, -b, -d, -q and -s options. Add common examples how to use kwboot. Add information about Armada 38x BootROM bug for debug console mode and how to workaround it. Signed-off-by:
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Add all supported Armada SoCs and document -b and -d options in usage. Signed-off-by:
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Marvell BootROM recognize only '\b' byte as backspace. Use terminfo for retrieving current backspace sequence and replace any occurrence of backspace sequence by the '\b' byte. Reading terminfo database is possible via tigetstr() function from system library libtinfo.so.*. So link kwboot with -ltinfo. Normally terminfo functions are in <term.h> system header file. But this header file conflicts with U-Boot "termios_linux.h" header file. So declare terminfo functions manually. Signed-off-by:
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-d option is currently broken. In most cases BootROM does not detect this message pattern. For sending debug message pattern it is needed to do same steps as for boot message pattern. Implement sending debug message pattern via same separate thread like it is for boot message pattern. Checking if BootROM entered into UART debug mode is different than detecting UART boot mode. When in boot mode, BootROM sends xmodem NAK bytes. When in debug mode, BootROM activates console echo and reply back every written byte (extept \r\n which is interpreted as executing command and \b which is interpreting as removing the last sent byte). So in kwboot, check that BootROM send back at least 4 debug message patterns as a echo reply for debug message patterns which kwboot is sending in the loop. Then there is another observation, if host writes too many bytes (as command) then BootROM command line buffer may overflow after trying to execute such long command. To workaround this overflow, it is enough to remove bytes from the input line buffer by sending 3 \b bytes for every sent character. So do it. With this change, it is possbile to enter into the UART debug mode with kwboot -d option. Signed-off-by:
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After BootROM successfully detects boot message pattern on UART it waits until host stop sending data on UART. For example Armada 385 BootROM requires that host does not send anything on UART at least 24 ms. If host is still sending something then BootROM waits (possibly infinitely). BootROM successfully detects boot message pattern if it receives it in small period of time after power on. So to ensure that host put BootROM into UART boot mode, host must send continuous stream of boot message pattern with a small gap (for A385 at least 24 ms) after series of pattern. But this gap cannot be too often or too long to ensure that it does not cover whole BootROM time window when it is detecting for boot message pattern. Therefore it is needed to do following steps in cycle without any delay: 1. send series of boot message pattern over UART 2. wait until kernel transmit all data 3. sleep small period of time At the same time, host needs to monitor input queue, data received on the UART and checking if it contains NAK byte by which BootROM informs that xmodem transfer is ready. But it is not possible to wait until kernel transmit all data on UART and at the same time in the one process to also wait for input data. This is limitation of POSIX tty API and also by linux kernel that it does not provide asynchronous function for waiting until all data are transmitted. There is only synchronous variant tcdrain(). So to correctly implement this handshake on systems with linux kernel, it is needed to use tcdrain() in separate thread. Implement sending of boot message pattern in one thread and reading of reply in the main thread. Use pthread library for threads. This change makes UART booting on Armada 385 more reliable. It is possible to start kwboot and power on board after minute and kwboot correctly put board into UART boot mode. Old implementation without separate thread has an issue that it read just one byte from UART input queue and then it send 128 message pattern to the output queue. If some noise was on UART then kwboot was not able to read BootROM response as its input queue was just overflowed and kwboot was sending more data than receiving. This change basically fixed above issue too. Signed-off-by:
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Function kwboot_debugmsg() is always called with kwboot_msg_debug as msg and function kwboot_bootmsg() with kwboot_msg_debug as msg. Function kwboot_bootmsg() is never called with NULL msg. Simplify, cleanup and remove dead code. No functional change. Signed-off-by:
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Variable msg_req_delay is set but never used. So completely remove it. Signed-off-by:
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Failure of kwboot_tty_send() and tcflush() functions is fatal, it does not make sense to continue. So return error back to the caller like in other places where are called these functions. Signed-off-by:
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Commit 369e5326 ("ddr: marvell: a38x: allow board specific ODT configuration") added the odt_config member to struct mv_ddr_topology_map ahead of the clk_enable and ck_delay members. This means that any boards that configured either of clk_enable or ck_delay needed to have their board topology updated. This affects the x530 and clearfog boards. Other A38x boards don't touch any of the trailing members of mv_ddr_topology_map so don't need updating. Fixes: 369e5326 ("ddr: marvell: a38x: allow board specific ODT configuration") Signed-off-by:
Chris Packham <judge.packham@gmail.com> Acked-by:
Baruch Siach <baruch@tkos.co.il> Reviewed-by:
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Commit 5534fb4f ("arm64: a37xx: pinctrl: Correct PWM pins definitions") introduced bogus definitions os PWM pins: all 4 pins have index 11, instead of having indexes 11, 12, 13, 14. Fix this. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
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Replace null pointer by pointer to device registers when calling armada38x_rtc_write. Signed-off-by:
Francois Berder <fberder@outlook.fr> Reviewed-by:
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The a3700_fdt_fix_pcie_regions() function still computes nonsense. It computes the fixup offset from the PCI address taken from the first row of the "ranges" array, which means that: - PCI address must equal CPU address (otherwise the computed fix offset will be wrong), - the first row must contain the lowest address. This is the case for the default device-tree, which is why we didn't notice it. It also adds the fixup offset to all PCI and CPU addresses, which is wrong. Instead: 1) The fixup offset must be computed from the CPU address, not PCI address. 2) The fixup offset must be computed from the row containing the lowest CPU address, which is not necessarily contained in the first row. 3) The PCI address - the address to which the PCIe controller remaps the address space as seen from the point of view of the PCIe device - must be fixed by the fix offset in the same way as the CPU address only in the special case when the CPU adn PCI addresses are the same. Same addresses means that remapping is disabled, and thus if we change the CPU address, we need also to change the PCI address so that the remapping is still disabled afterwards. Consider an example: The ranges entries contain: PCI address CPU address 70000000 EA000000 E9000000 E9000000 EB000000 EB000000 By default CPU PCIe window is at: E8000000 - F0000000 Consider the case when TF-A moves it to: F2000000 - FA000000 Until now the function would take the PCI address of the first entry: 70000000, and the new base, F2000000, to compute the fix offset: F2000000 - 70000000 = 82000000, and then add 8200000 to all addresses, resulting in PCI address CPU address F2000000 6C000000 6B000000 6B000000 6D000000 6D000000 which is complete nonsense - none of the CPU addresses is in the requested window. Now it will take the lowest CPU address, which is in second row, E9000000, and compute the fix offset F2000000 - E9000000 = 09000000, and then add it to all CPU addresses and those PCI addresses which equal to their corresponding CPU addresses, resulting in PCI address CPU address 70000000 F3000000 F2000000 F2000000 F4000000 F4000000 where all of the CPU addresses are in the needed window. Fixes: 4a82fca8 ("arm: a37xx: pci: Fix a3700_fdt_fix_pcie_regions() function") Signed-off-by: -
Enable ext4 write support in Turris Omnia's defconfig. Some users find it useful. Signed-off-by:
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Use "MVPCIE_" prefix instead of generic "PCIE_" prefix for pci_mvebu.c specific macros. Define offset macros for Root Port registers and use standard register macros from pci.h when accessing Root Port registers. Signed-off-by:
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Macro SELECT() is unused and struct mvebu_pcie field lane_mask is unused too. Remove them. Signed-off-by:
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