- Sep 13, 2022
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- Enable ASPEED SPI controller driver. - Enable SPI flash memory configurations. - Enable configurations for SPI flash manufacturers supported on both ASPEED AST2500 and AST2600 AVL. Signed-off-by:Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
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Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: -
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group. On AST2500 EVB, FWSPICS1 can be supported by default. An extra jumper, J45, should be configured before enabling SPI1CS1. Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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User can get correct HCLK frequency during driver probe stage by adding the following configuration in the device tree. "clocks = <&scu ASPEED_CLK_AHB>". Signed-off-by:
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Tom Rini authored
Merge tag 'xilinx-for-v2023.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2023.01-rc1 cmd: - bdinfo - guard LMB code to run only when LMB is enabled timer: - convert arm twd timer to DM power-domain: - Skip loading config object for Versal xilinx: - Fix logic when dfu_alt_info is generated - Define only mmc devnum not partition - Add xlnx prefix to GEM compatible string - Add missing tca6416 to zynqmp SC - vck190 - Add env redund offset - Enable CMD_GREPENV/SETEXPR by default - Move board_get_usable_ram_top() to common location - Add support for SOC detection net/gem: - Check rate before setting it up microblaze: - drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE - Show cache size in bdinfo spi: - cadence_qspi: driver updates - zynqmp_gqspi: driver updates - zynqmp_gqspi: Add tap delays for Versal zynq: - Enable mkeficapsule compilation - Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info - Align bss and end of u-boot image to 64bits - Align qspi node name with Linux kernel - DT: List OCM memory zynqmp: - Fix AES cache handling with a user provided key - SOM: Add mtd partition for secure OS storage area - Add ref_clk property for REFCLKPER calculation - Fix mdio bus description for vck190-sc xilinx-mini: - Remove unneeded configs - Disable LMB versal: - Enable i2c mux pca954x by default - Define CONFIG_CQSPI_REF_CLK - Enable power domain driver - Enable zynqmp_gqspi driver
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Tom Rini authored
To quote the author: This series makes a further attempt to get closer to having all tests run in parallel. It introduces a new 'make pcheck' option which runs tests in parallel, skipping those that are not compatible. A number of fixes are included for existing tests. The vboot test is updated to only run a single scenario in 'quick' mode. This makes use of pytest's parallel-testing features. The resulting times (including incremental building with LTO) on a 16-core machine are as follows: make pcheck - 1 minute 6 seconds make qcheck - 3 minutes make check - 5 minutes 15 seconds Note that this is not a fair comparison, since 'make pcheck' omits a number of tests, even more than 'make qcheck'.
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Michal Simek authored
Code supports board detection based on information available in EEPROM in legacy or FRU format. But this is not enough for emulation and simulation systems which are lacking these identification EEPROMs. But SOC itself has normally registers for SOC identification. Based on them it is possible to compose detected name. That's why prepare infrastructure in common location for SOC platform detection which is called before board platform detection. SOC platform detection shouldn't detect real silicon and should fallback to current existing mechanism to identify boards based on EEPROMs. Signed-off-by:
Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/329a8da338927b082e26a958bf69bb18af072420.1662460837.git.michal.simek@amd.com
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Michal Simek authored
Current behavior is that eth_phy_get_mdio_bus Net: FEC: can't find phy-handle ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Net: ZYNQ GEM: ff0b0000, mdio bus ff0b0000, phyaddr 0, interface sgmii eth0: ethernet@ff0b0000 Signed-off-by:
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Michal Simek authored
Description OCM with mmio-sram driver. In 99% use cases OCM is mapped high that's why it is placed on fixed location. Signed-off-by:
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Michal Simek authored
Nodes should follow generic rules where compatible and reg properties should be listed on the top of node. That's why sync it up. Signed-off-by:
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Ashok Reddy Soma authored
Versal supports gqspi ip, so enable zynqmp_gqspi driver for Versal platforms. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-7-ashok.reddy.soma@amd.com Signed-off-by:
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Ashok Reddy Soma authored
Few lines are extented to next line though they can fit in 80 character limit, align them to single line. No functional change. Signed-off-by:
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Ashok Reddy Soma authored
As the flash sizes are increasing day by day, QSPI can have devices of size > 512MB. In qspi driver we are trying to read all the data at once using DMA. The DMA descriptor destination size is only 29bits long. QSPIDMA_DST_SIZE 0xFF0F0804 BITS: 1:0 Reserved to keep word alignment BITS: 28:2 Number of 4-byte words the DMA will transfer BITS: 31:29 Reserved: Returns 0 when read, writes ignored So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes. Anything above will overflow this register and will ignore higher bits above 29 bits. Change the DMA functionality if the requested size is greater than or equal to 512MB to read 256MB chunks. Signed-off-by:
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Ashok Reddy Soma authored
Add support for io-mode transfers. This is necessary for UBIFS to work properly with spi-nor devices. The driver will work in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by:
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Michal Simek authored
GQSPI driver is using it but this function is never called for Versal because it is removed by linker. But function should be declared to avoid this build warning: drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay': drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function 'zynqmp_mmio_write' [-Wimplicit-function-declaration] 378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Ashok Reddy Soma authored
Add tap delays for Versal platform and re-align the tapdelays code. Signed-off-by:
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Ashok Reddy Soma authored
As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by:
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Ashok Reddy Soma authored
In cadence_spi_read_id we are using STIG mode to read flash id's. Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data bus width properly before cadence_qspi_apb_command_read(). Signed-off-by:
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Ashok Reddy Soma authored
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset the flash device. Looks like there is a mistake in previous series of patches where it is defined as cadence_spi_versal_flash_reset() but called as cadence_qspi_versal_flash_reset. Since there is a weak function defined with the same name this issue was not caught. Fix the issue by renaming cadence_spi_versal_flash_reset as cadence_qspi_versal_flash_reset(). Signed-off-by:
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Ovidiu Panait authored
Allow bdinfo command to print icache/dcache information: U-Boot-mONStR> bdinfo boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x04000000 -> size = 0x04000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 9600 bps relocaddr = 0x07f76000 reloc off = 0x02f76000 Build = 32-bit current eth = unknown ethaddr = (not set) IP addr = <NULL> fdt_blob = 0x07fec7e0 new_fdt = 0x00000000 fdt_size = 0x00000000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0 reserved.cnt = 0x1 reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0 devicetree = embed icache = 32 KiB icache line = 4 Bytes dcache = 32 KiB dcache line = 4 Bytes Signed-off-by:
Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com Signed-off-by:
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Ovidiu Panait authored
Add bdinfo_print_size() helper to display size variables (such as cache sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB", "xxx MiB", "xxx GiB", etc as needed; Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Jason Liu <jason.hui.liu@nxp.com> Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com Signed-off-by:
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Ovidiu Panait authored
Check snprintf() return value for errors. Make microblaze_cpu_get_desc() directly return snprintf() error code if ret < 0. Otherwise, if the return value is greater than or equal to size, the resulting string is truncated, so return -ENOSPC. Fixes: 816226d2 ("cpu: add CPU driver for microblaze") Signed-off-by:
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Ovidiu Panait authored
These macros are not used anymore in microblaze code since commit f113d7d3 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them. Fixes: f113d7d3 ("Convert CONFIG_SPL_STACK to Kconfig") Signed-off-by:
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Michal Simek authored
On QEMU setting rate for fixed clock is failing. That's why check a rate first if the rate is the same there is no need to ask for the change. Signed-off-by:
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Michal Simek authored
There shouldn't be a reason to have LMB on for these configurations. LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs: zynqmp: Disable LMB for mini u-boot"). Signed-off-by: -
Michal Simek authored
The commit ce39ee28 ("zynqmp: Do not place u-boot to reserved memory location") adds functionality for ZynqMP to read reserved memory node and do not place U-Boot to reserved location. This functionality is generic across all Xilinx SOCs that's why move it to common location to be used by all Xilinx SOCs. On zynq platform this is also fixing issue where U-Boot was placed to locating which was reserved already which ends up with error message "ERROR: reserving fdt memory region failed (addr=30000000 size=10000000 flags=4)" which is shown when bdinfo is called. Tested on vck190, zcu102, zc706 and kc705 to cover all platforms. Signed-off-by:
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Michal Simek authored
The main reason is that DT memory reserved code is expecting DT to be 64bit aligned. For more information take a look at commit 5bd5ee02 ("xilinx: zynqmp: Check that DT is 64bit aligned"). Signed-off-by:
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Michal Simek authored
Enable both of these commands in Xilinx SoCs to be able to use them in boot scripts. Signed-off-by:
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T Karthik Reddy authored
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env variables is overwriting data at 0 offset, which is wrong. So add default redund env offset for Zynq, ZynqMP, Versal and microblaze platforms. Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE). In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000. Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of ENV_IS_IN_SPI_FLASH config. Below table specifies platform specific env and env redund offsets. PLAT ENV_OFFSET ENV_OFFSET_REDUND ---- ---------- ----------------- ZYNQ 0xE0000 0xE40000 ZYNQMP 0x1E00000 0x1E80000 VERSAL 0x7F40000 0x7F00000 MICROBLAZE 0x1080000 0x10C0000 Signed-off-by:
T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by:
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Piyush Mehta authored
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ calculation. This property configure correct value for SOF/ITP counter and period of ref_clk. This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores. Signed-off-by:
Piyush Mehta <piyush.mehta@amd.com> Signed-off-by:
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Michal Simek authored
Add missing tca6416 i2c gpio controller to SC dts file. Signed-off-by:
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Harini Katakam authored
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx prefix. Add this new compatible string and retain the existing string for compatibility with uboot drivers. Signed-off-by:
Harini Katakam <harini.katakam@amd.com> Signed-off-by:
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Amit Kumar Mahapatra authored
Update MTD partitions of Kria device trees to allocate 128KB of QSPI memory for secure OS. Increased "SHA256" partition size & changed starting address of "User" partition to accommodate the new partition "Secure OS Storage" Signed-off-by:
Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by:
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Michal Simek authored
The commit 53b40636 ("DFU: Check the number of arguments and argument string strictly") added strict control over string that 0:1 partition definition is not valid anymore that's why use only device number without partition ID. Device is specified by 2nd parameter and partition by 3rd. Signed-off-by:
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Michal Simek authored
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME stores the name of firmware file to be loaded by SPL. Name can be selected via Kconfig that's why use the macro. Signed-off-by:
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Michal Simek authored
Generate dfu_alt_info only when it is not defined. Signed-off-by:
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Michal Simek authored
Zynq can use efi capsule infrastructure that's why enable it by default. For capsule generation for zynq you can use: pushd spl ../tools/mkeficapsule -g "1ba29a15-9969-40aa-b424-e86121618664" boot.bin \ --index 1 ../capsule1.bin popd ./tools/mkeficapsule -g "1a5178f0-87d3-4f36-ac63-3b31a23be305" u-boot.img \ --index 2 capsule2.bin Signed-off-by:
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Ashok Reddy Soma authored
With commit 55b3ba4c ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig. The static value via Kconfig is a fallback option in case of clock framework is not enabled or fails for some reason. Signed-off-by:
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Ashok Reddy Soma authored
Enable power domain driver to request node for all the IP's that are enabled in DT. Signed-off-by:
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Ashok Reddy Soma authored
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip loading config object for Versal until support is added. Signed-off-by:
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