- Sep 13, 2022
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This adds support for the dirmap API to the spi-nor subsystem, as introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use spi-mem dirmap API"). This patch is synchronize from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is df5c21002cf4. Signed-off-by:Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by:
Sean Anderson <seanga2@gmail.com> Acked-by:
Pratyush Yadav <p.yadav@ti.com>
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This adds the dirmap API originally introduced in Linux commit aa167f3fed0c ("spi: spi-mem: Add a new API to support direct mapping"). This also includes several follow-up patches and fixes. Changes from Linux include: * Added Kconfig option * Changed struct device to struct udevice * Changed struct spi_mem to struct spi_slave This patch is obtained from the following patch https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/ The corresponding Linux kernel SHA1 is aa167f3fed0c. Signed-off-by: -
Although AST2400 is EOL officially, in order to achieve sustainability and completeness, AST2400 part is added. For AST2400, - Five CSs are supported by FMC controller. - SPI1 controller only supports single CS and there is no address segment address register. The CE control register of SPI1 is located at the offset 0x04 and the 4-byte address mode control bit is bit 13 of this register. Signed-off-by: -
Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface for AST2500 and AST2600 platform. There are three SPI memory controllers embedded in an ASPEED SoC. - FMC: Named as Firmware Memory Controller. After AC on, MCU ROM fetches initial device boot image from FMC chip select(CS) 0. - SPI1: Play the role of a SPI Master controller. Or, there is a dedicated path for HOST(X86) to access its BIOS flash mounted under BMC. spi-aspeed-smc.c implements the control sequence when SPI1 is a SPI master. - SPI2: It is a pure SPI flash controller. For most scenarios, flashes mounted under it are for pure storage purpose. ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode. Three types of command mode are supported, normal mode, command read/write mode and user mode. - Normal mode: Default mode. After power on, normal read command 03h or 13h is used to fetch boot image from SPI flash. - AST2500: Only 03h command can be used after power on or reset. - AST2600: If FMC04[6:4] is set, 13h command is used, otherwise, 03h command. The address length is decided by FMC04[2:0]. - Command mode: SPI controller can send command and address automatically when CPU read/write the related remapped or decoded address area. The command used by this mode can be configured by FMC10/14/18[23:16]. Also, the address length is decided by FMC04[2:0]. This mode will be implemented in the following patch series. - User mode: It is a traditional and pure SPI operation, where SPI transmission is controlled by CPU. It is the main mode in this patch. Each SPI controller in ASPEED SoC has its own decoded address mapping. Within each SPI controller decoded address, driver can assign a specific address region for each CS of a SPI controller. The decoded address cannot overlap to each other. With normal mode and command mode, the decoded address accessed by the CPU determines which CS is active. When user mode is adopted, the CS decoded address is a FIFO, CPU can send/receive any SPI transmission by accessing the related decoded address for the target CS. This patch only implements user mode initially. Command read/write mode will be implemented in the following patches. Signed-off-by: -
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group. On AST2500 EVB, FWSPICS1 can be supported by default. An extra jumper, J45, should be configured before enabling SPI1CS1. Signed-off-by:
Cédric Le Goater <clg@kaod.org>
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User can get correct HCLK frequency during driver probe stage by adding the following configuration in the device tree. "clocks = <&scu ASPEED_CLK_AHB>". Signed-off-by:
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Ashok Reddy Soma authored
Few lines are extented to next line though they can fit in 80 character limit, align them to single line. No functional change. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@amd.com> Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com Signed-off-by:
Michal Simek <michal.simek@amd.com>
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Ashok Reddy Soma authored
As the flash sizes are increasing day by day, QSPI can have devices of size > 512MB. In qspi driver we are trying to read all the data at once using DMA. The DMA descriptor destination size is only 29bits long. QSPIDMA_DST_SIZE 0xFF0F0804 BITS: 1:0 Reserved to keep word alignment BITS: 28:2 Number of 4-byte words the DMA will transfer BITS: 31:29 Reserved: Returns 0 when read, writes ignored So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes. Anything above will overflow this register and will ignore higher bits above 29 bits. Change the DMA functionality if the requested size is greater than or equal to 512MB to read 256MB chunks. Signed-off-by:
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Ashok Reddy Soma authored
Add support for io-mode transfers. This is necessary for UBIFS to work properly with spi-nor devices. The driver will work in IO mode when "has-io-mode" is passed from device tree instead of DMA. Signed-off-by:
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Ashok Reddy Soma authored
Add tap delays for Versal platform and re-align the tapdelays code. Signed-off-by:
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Ashok Reddy Soma authored
As per driver model we should enumerate plat structure only in of_to_plat() and should be used only in probe(). Copy required plat structure info into priv structure in probe() and use priv structure across the driver. So replace plat with priv structure across the driver. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com Signed-off-by:
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Ashok Reddy Soma authored
In cadence_spi_read_id we are using STIG mode to read flash id's. Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data bus width properly before cadence_qspi_apb_command_read(). Signed-off-by:
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Ashok Reddy Soma authored
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset the flash device. Looks like there is a mistake in previous series of patches where it is defined as cadence_spi_versal_flash_reset() but called as cadence_qspi_versal_flash_reset. Since there is a weak function defined with the same name this issue was not caught. Fix the issue by renaming cadence_spi_versal_flash_reset as cadence_qspi_versal_flash_reset(). Signed-off-by:
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Ovidiu Panait authored
Check snprintf() return value for errors. Make microblaze_cpu_get_desc() directly return snprintf() error code if ret < 0. Otherwise, if the return value is greater than or equal to size, the resulting string is truncated, so return -ENOSPC. Fixes: 816226d2 ("cpu: add CPU driver for microblaze") Signed-off-by:
Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com Signed-off-by:
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Michal Simek authored
On QEMU setting rate for fixed clock is failing. That's why check a rate first if the rate is the same there is no need to ask for the change. Signed-off-by:
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Ashok Reddy Soma authored
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip loading config object for Versal until support is added. Signed-off-by:
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- Sep 12, 2022
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Stefan Herbrechtsmeier authored
The drivers informs the user that a post config was not run after FPGA configuration. This message is unnecessary in SPL because the ps7_post_config function is called via spl_board_prepare_for_boot function before jump_to_image_no_args function from board_init_r function. Signed-off-by:
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220808145331.24723-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by:
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Stefan Herbrechtsmeier authored
Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by:
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- Aug 26, 2022
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We can check if the message was acknowledged in the common ti_sci_do_xfer() which lets us remove it from after each call to this function. This simplifies the code and reduces binary size. Signed-off-by:Andrew Davis <afd@ti.com>
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The inline hint is not needed here, the compiler will do the right thing based on if we are compiling for speed or for code size. In this case the inline causes this function to be placed inside each callsite which is not the right thing to do for either speed nor size. There is no performance benefit to this due to the larger function size reducing cache locality, but there is a huge size penalty. Remove inline keyword. Signed-off-by: -
We don't need to print the same message in every location, just print it in the function that fails and remove all the extra message printouts. Signed-off-by: -
This ti_sci_do_xfer() function already prints out the reason for the failure, and the caller of each of these functions should also notify the user of the failed task. Remove this extra level of error message. Signed-off-by: -
Currently for all Qcom SoCs/boards there are separate compatibles for GPIO and pinctrl. But this is inconsistent with official (upstream) Linux bindings which requires only a single compatible "qcom,<SoC name>-pinctrl" and there is no such compatible property as "qcom,tlmm-<SoC name>". So fix this inconsistency for Qcom SoCs in order to comply with upstream DT bindings. This is done via removing compatibles from "msm_gpio" driver and via binding to "msm_gpio" driver from pinctrl driver in case "gpio-controller" property is specified for pinctrl node. Suggested-by:
Stephan Gerhold <stephan@gerhold.net> Signed-off-by:
Sumit Garg <sumit.garg@linaro.org>
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GPIO LV (low voltage)/MV (medium voltage) subtypes have different features and register mappings than 4CH/8CH subtypes. Add support for LV and MV subtypes. With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible which requires support for GPIO MV subtype. Signed-off-by: -
Since both pm8916.c and pm8916_gpio.c are already supporting multiple Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and qcom_pmic_gpio.c respectively. Also, these driver can be extended to support additional functionality if required for other Qcom SoCs. Along with this import latest DT binding: qcom,spmi-pmic.txt from Linux kernel and thereby remove pm8916.txt. Signed-off-by: -
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Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: -
QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers. Signed-off-by: -
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- Aug 23, 2022
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The gpio-button driver depends on DM_GPIO, add it to Kconfig to avoid build errors. Signed-off-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Stefan Roese <sr@denx.de>
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Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
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- Aug 22, 2022
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During compilation gcc throws warning: drivers/mtd/nand/raw/fsl_elbc_nand.c: In function ‘fsl_elbc_nand_probe’: drivers/mtd/nand/raw/fsl_elbc_nand.c:841:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev); ^ Fix it by using dev_read_addr_ptr() function which returns pointer instead of dev_read_addr() which returns integer type. Signed-off-by:Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by:
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Subpage write support for freescale eLBC NAND controller driver is implemented in U-Boot and was fixes in the commit d3963721 ("nand: Sync with Linux v4.1"). So remove NAND_NO_SUBPAGE_WRITE flag from the fsl_elbc_nand.c driver. This partially revert commit cb04c772 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers"), only eLBC driver part. With this change U-Boot with default settings can read from NAND UBIFS image created on Linux with Linux default settings. Prior this change U-Boot was unable to read from NAND UBIFS images created with Linux default settings due to differnet UBI geometry. Linux kernel fsl_elbc_nand.c driver also does not set NAND_NO_SUBPAGE_WRITE flag and has implemented subpage write support. Fixes: cb04c772 ("nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers") Fixes: d3963721 ("nand: Sync with Linux v4.1") Signed-off-by:
Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by:
Michael <Trimarchi<michael@amarulasolutions.com> Signed-off-by:
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Michael Trimarchi authored
Upstream linux commit 8fc82d456e40a0. On some nand controllers with hw-ecc the controller code wants to know the ecc strength and size and having these as 0, 0 is not accepted. Specifying these in devicetree is possible but undesirable as the nand may be different in different production runs of the same board, so it is better to get this info from the nand id where possible. This commit adds code to read the ecc strength and size from the nand for Samsung extended-id nands. This code is based on the info for the 5th id byte in the datasheets for the following Samsung nands: K9GAG08U0E, K9GAG08U0F, K9GAG08X0D, K9GBG08U0A, K9GBG08U0B. These all use these bits in the exact same way. Signed-off-by:
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Michael Trimarchi authored
Upstream linux commit 7bb427990ee364. Rename the function to match this new behavior. NOTE: fix nand_detect/nand_get_flash_type parameters in mxs_nand_spl. This code seems never executed by any board as alternative for nand detect Signed-off-by:
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Michael Trimarchi authored
Upstream linux commit 4722c0e958e636. The returned "type" is never used in nand_scan_ident() and spl code Make nand_get_flash_type() simply return an integer value in order to avoid unnecessary ERR_PTR/PTR_ERR dance. Signed-off-by:
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Michael Trimarchi authored
Upstream linux commit 8cfb9ab68f9070. Drop the 's' at the end of nand_manufacturers since the struct is actually describing a single manufacturer, not a manufacturer table. Signed-off-by:
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- Aug 21, 2022
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The kmtegr1 board is out of maintenance and can be removed. As it is the only board in the tree using MPC8309 the support for this CPU is dropped completely. Signed-off-by:Holger Brunck <holger.brunck@hitachienergy.com>
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Tom Rini authored
The deadline for DM_ETH migration passed 2 years ago. Now that platforms which cannot be migrated have been either removed or had drivers disabled, and platforms that needed minor help to migrate have been forcefully migrated, we can complete the migration. This entails select'ing DM_ETH under NETDEVICES, and then removing now extraneous depends on lines. In a few places, we can now either remove options or just simplify later dependencies. Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Rini <trini@konsulko.com> Acked-by:
Ramon Fried <rfried.dev@gmail.com>
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Tom Rini authored
As this driver has been converted to DM_ETH and the migration deadline is 2 years passed, remove the legacy code and callers. Cc: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by:
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