- Dec 18, 2020
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https://gitlab.denx.de/u-boot/custodians/u-boot-amlogicTom Rini authored
- fix Odroid-C4 soft-reboot caused by bad setup of SDCard VDD regulator
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Marek Szyprowski authored
For the proper reboot Odroid-C4 board requires to switch TFLASH_VDD_EN pin to the high impedance mode, otherwise the board is stuck in the middle of loading early stages of the bootloader from SD card. This can be achieved by using the OPEN_DRAIN flag instead if the ACTIVE_HIGH, what will leave the pin in input to achieve high state (pin has the pull-up) and solve the issue. Suggested-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com> Acked-by:
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Add Micron MT25QL01G flash, used on AST2600 board. Signed-off-by:
Hongwei Zhang <hongweiz@ami.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com>
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Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by:
Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by:
Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by:
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This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix Bit. Signed-off-by:
Sean Anderson <seanga2@gmail.com> Acked-by:
Rick Chen <rick@andestech.com> Reviewed-by:
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The designware ssi device has "broken" chip select behaviour [1], and needs specific manipulation to use the built-in chip select. The existing fix is to use an external GPIO for chip select, but typically the K210 has SPI3 directly connected to a flash chip with dedicated pins. This makes it impossible to use the spi_xfer function to use spi, since the CS is de-asserted in between calls. This patch adds an implementation of exec_op, which gives correct behaviour when reading/writing spi flash. This patch also rearranges the headers to conform to U-Boot style. [1] https://lkml.org/lkml/2015/12/23/132 Signed-off-by:
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This documentation has been taken from Linux commit 3d7db0f11c7a ("spi: dw: Refactor mid_spi_dma_setup() to separate DMA and IRQ config"), immediately before the file was deleted and replaced with a yaml version. Additional compatible strings from newer versions have been added, as well as a few U-Boot-specific ones. Signed-off-by: -
CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/ Signed-off-by:
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This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by:
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This should reduce the size of the struct, and also groups more similar fields together. Signed-off-by:
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This function does nothing but wrap dw_write. Signed-off-by:
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A few registers had slightly different names from what is in the datasheet. Signed-off-by:
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Using an fdt-specific function causes problems when compiled with a live tree. Signed-off-by:
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This property is named differently than other SPI drivers with the same property, as well as the property as used in Linux. Signed-off-by:
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This allows different log levels to be enabled or disabled depending on the desired level of verbosity. In particular, it allows for general debug information to be printed while excluding more verbose logging which may interfere with timing. Signed-off-by:
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The resting state of MOSI is high when nothing is driving it. If we drive it low while recieving, it looks like we are transmitting 0x00 instead of transmitting nothing. This can confuse slaves (like SD cards) which allow new commands to be sent over MOSI while they are returning data over MISO. The return of MOSI from 0 to 1 at the end of recieving a byte can look like a start bit and a transmission bit to an SD card. This will cause the card to become out-of-sync with the SPI device, as it thinks the device has already started transmitting two bytes of a new command. The mmc-spi driver will not detect the R1 response from the SD card, since it is sent too early, and offset by two bits. This patch fixes transfer errors when using SD cards with dw spi. Signed-off-by:
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U-Boot is able to erase bad mtd blocks on raw nand devices, but this is not true for spinand flashes. Lets enable this feature for spinand flashes as well. This is extemelly useful for flash testing. Signed-off-by:Mikhail Kshevetskiy <mikhail.kshevetskiy@oktetlabs.ru>
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Currently when marking a block, we use spinand_erase_op() to erase the block before writing the marker to the OOB area. Doing so without waiting for the operation to finish can lead to the marking failing silently and no bad block marker being written to the flash. In fact we don't need to do an erase at all before writing the BBM. The ECC is disabled for raw accesses to the OOB data and we don't need to work around any issues with chips reporting ECC errors as it is known to be the case for raw NAND. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by:Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schrempf@kontron.de
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When writing the bad block marker to the OOB area the access mode should be set to MTD_OPS_RAW as it is done for reading the marker. Currently this only works because req.mode is initialized to MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for req.mode != MTD_OPS_AUTO_OOB. Fix this by explicitly setting req.mode to MTD_OPS_RAW. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: -
For reading and writing the bad block markers, spinand->oobbuf is currently used as a buffer for the marker bytes. During the underlying read and write operations to actually get/set the content of the OOB area, the content of spinand->oobbuf is reused and changed by accessing it through spinand->oobbuf and/or spinand->databuf. This is a flaw in the original design of the SPI NAND core and at the latest from 13c15e07eedf ("mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache") on, it results in not having the bad block marker written at all, as the spinand->oobbuf is cleared to 0xff after setting the marker bytes to zero. To fix it, we now just store the two bytes for the marker on the stack and let the read/write operations copy it from/to the page buffer later. Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Cc: stable@vger.kernel.org Signed-off-by: -
Spelling. Signed-off-by:
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u_boot should be u-boot Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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According to the mx25l12805d datasheet it supports using 4K or 64K sectors. So lets add the SECT_4K to enable 4K sector usage. Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by:
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Add Winbond W25M512JW flash device description. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
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Add Winbond W25M512JV flash device description. Linux already has the flash entry present. A snippet below: { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024...}, Signed-off-by: -
Define LOG_CATEGORY and change printf and pr_* to dev_ (when dev is available) or log_ macro. This patch adds the support of logging feature with log command (filtering, display of device name in trace) and allows to suppress traces via the syslog driver. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
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Jagan Teki authored
Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Ludwig Zenz <lzenz@dh-electronics.de> Cc: Andreas Geisreiter <ageisreiter@dh-electronics.de> Signed-off-by: -
Jagan Teki authored
Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: -
Jagan Teki authored
Enable DM_SPI/DM_SPI_FLASH with associated config options. Build fine, but not tested. Cc: Uri Mashiach <uri.mashiach@compulab.co.il> Signed-off-by:
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- Dec 16, 2020
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:Tom Rini <trini@konsulko.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini authored
- Update cmdline parameter to be an env var in zimage boot - Various minor fixes for Intel Edison board
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Remove the redundant setting for USB_RX_EARLY_SIZE. Besides, for RTL8153B, it is necessary to notify the hardware of the changes of the aggregation settings. Signed-off-by:Hayes Wang <hayeswang@realtek.com>
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The r8152_eth_probe() may allocate a memory for ss->dev_priv. It has to be freed if r8152_eth_probe() fails finally. Signed-off-by: -
For bulk IN transfer, the codes will set ISP flag to request event TRB being generated by xHC for the case of short packet. So when encountering buffer-cross-64K-boundary (which we will divide payload and enqueuqe more than 1 transfer TRB), and the first TRB ends up with a short packet condition it will trigger an short packet code transfer event per that flag and cause more than 1 event TRB generated for this transfer. However, current codes will only handle the first transfer event TRB then mark current transfer completed, causing next transfer failure due to event TRB mis-match. Such issue has been observed on some Layerscape platforms (LS1028A, LS1088A, etc) with USB ethernet device. This patch adds a loop to make sure the event TRB for last transfer TRB has been handled in time. Signed-off-by:
Ran Wang <ran.wang_1@nxp.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
DM is the modern default approach for the drivers in U-Boot. It also allows to configure code via Device Tree. Move Intel Edison to use DM_USB_GADGET and drop hard coded values. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
Use generic Synopsys DesignWare 3 driver on Intel Edison. For now it's just a stub which allows future refactoring. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
The platforms based on Intel Tangier may have different requirements how to create bootloader bundle to supply to a device. Currently the BINMAN approach is for Intel Edison only. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Like in the rest of x86 boards append CPU to the board compatible string. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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