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  1. Nov 07, 2022
    • Chris Packham's avatar
      arm: mvebu: Add RD-AC5X board · 6cc8b5db
      Chris Packham authored and Stefan Roese's avatar Stefan Roese committed
      
      The RD-AC5X-32G16HVG6HLG-A0 development board main components and
      features include:
      * Main 12V/54V power supply
      * 270 Gbps throughput packet processor on the main board
      * DDR4:
        * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
        * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
        * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
      * 16GB eMMC (Samsung KLMAG1JETD-B041006)
      * 16MB SPI NOR(GD25Q127C)
      * 32 x 1000 Base-T interfaces
      * 16 x 2500 Base-T interfaces
        * SR1: 88E2540*4
        * SR2: 88E2580*1+88E2540*2
      * Six (6) x 25G Base-R SFP28 interfaces
      * One (1) x RJ-45 console connector, interfacing to the on board UART
      * One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
      * One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
      * One (1) x RJ-45 1G Base-T Management port, interfacing to the host
        port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
      * One (1) x Oculink port, interfacing to the PCIe port for external CPU
        connection
      * POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
        Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
        solution)
      * POE total power budget 780W
      * LED interfaces per network port/POE
      * LED interfaces (common) showing system status
      * PTP TC mode Supported (Reserved M.2 connector to support BC mode)
      
      Signed-off-by: default avatarChris Packham <judge.packham@gmail.com>
      6cc8b5db
    • This contributor prefers not to receive mails's avatar
      Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb · 87ac4b4b
      This contributor prefers not to receive mails authored and Stefan Roese's avatar Stefan Roese committed
      
      File name with pattern u-boot-spl* is used on all places except in kwb
      image for binary with SPL-only code. Combined binary with both SPL and
      proper U-Boot in other places has file name pattern u-boot-with-spl*.
      
      Make it consistent also for kwb image and rename u-boot-spl.kwb to
      u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.
      
      Also update documentation about file name changes.
      
      Signed-off-by: default avatarPali Rohár <pali@kernel.org>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      87ac4b4b
  2. Nov 03, 2022
  3. Nov 02, 2022
    • Daniel Schwierzeck's avatar
      MIPS: remove CONFIG_SYS_MHZ · e9dcd5b4
      Daniel Schwierzeck authored
      
      Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
      Remove code which depends on CONFIG_SYS_MHZ but where no board configs
      actually use that code.
      
      Signed-off-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
      Reviewed-by: default avatarStefan Roese <sr@denx.de>
      e9dcd5b4
    • Bin Meng's avatar
      treewide: Remove the unnecessary space before semicolon · ea253ad7
      Bin Meng authored and Tom Rini's avatar Tom Rini committed
      
      %s/return ;/return;
      
      Signed-off-by: default avatarBin Meng <bmeng@tinylab.org>
      ea253ad7
    • André Przywara's avatar
      highbank: scan into hb_sregs DT subnodes · 4849e2ed
      André Przywara authored and Tom Rini's avatar Tom Rini committed
      
      The DT used for Calxeda Highbank and Midway systems exposes a "system
      registers" block, modeled as a DT subnode.
      This includes several clocks, including the two fixed clocks for the
      main oscillator and timer.
      
      So far U-Boot was ignorant of this special construct (a "clocks" node
      within the "hb-sregs" node), as it didn't need the PLL clocks in there.
      But that also meant we lost the fixed clocks, which form the base for
      the UART baudrate generator and also the SP804 timer.
      
      To allow the generic PL011 and SP804 driver to read the clock rate,
      add a simple bus driver, which triggers the DT node discovery inside this
      special node. As we only care about the fixed clocks (we don't have
      drivers for the PLLs anyway), just ignore the address translation (for
      now).
      
      The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT
      snippet in question looks like:
      
      =======================
      	sregs@fff3c000 {
      		compatible = "calxeda,hb-sregs";
      		reg = <0xfff3c000 0x1000>;
      
      		clocks {
      			#address-cells = <1>;
      			#size-cells = <0>;
      
      			osc: oscillator {
      				#clock-cells = <0>;
      				compatible = "fixed-clock";
      				clock-frequency = <33333000>;
      			};
      			....
      		};
      	};
      =======================
      
      Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      4849e2ed
  4. Oct 31, 2022
  5. Oct 30, 2022
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