- Apr 06, 2022
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This may have different settings for SPL and TPL. Correct the condition. Signed-off-by:Simon Glass <sjg@chromium.org>
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If the buffer is empty and not allocated, then abuf_realloc() tries to copy invalid data. This happens because an incorrect change to use memdup() was added after the original code was written. Signed-off-by: -
At present the header file defines this function in SPL but the file may not actually be built. This causes a build error if the option is enabled. Fix the condition in the header file. Signed-off-by: -
The conversion to bintools broke the invocation of the utility, since the arguments are not correct. Fix it. Signed-off-by: -
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Tom Rini authored
- Add DM_PMIC support to TPS65217 and migrate some platforms to it. - mkimage verification fixes - DM rST fix, add missing flag when linking u-boot-elf.o
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We use Sphinx style comments to describe functions. Signed-off-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
If image backend provides verify_header callback then call it after writing image to disk. This ensures that written image is correct. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
Stefan Roese <sr@denx.de> Reviewed-by:
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rockchip header_v2 do not have a spl_hdr, so remove the verify. Signed-off-by:
Yi Liu <liuyi@rock-chips.com> Signed-off-by:
Kever Yang <kever.yang@rock-chips.com>
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fix compile error when using a little-endian to build with configs: sfr_nb4-ser_ram_defconfig comtrend_wap5813n_ram_defconfig comtrend_ar5387un_ram_defconfig comtrend_ct5361_ram_defconfig comtrend_vr3032u_ram_defconfig comtrend_ar5315u_ram_defconfig huawei_hg556a_ram_defconfig netgear_dgnd3700v2_ram_defconfig Signed-off-by:Du Huanpeng <dhu@hodcarrier.org>
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Heinrich Schuchardt authored
When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message alloc space exhausted 32 is the current maximum number of harts for machine virt in QEMU 7.0. Raise the default for SYS_MALLOC_F_LEN to 16 KiB. Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. Signed-off-by:Tom Rini <trini@konsulko.com> Reviewed-by:
Rick Chen <rick@andestech.com>
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Heinrich Schuchardt authored
Let CONFIG_TARGET_QEMU_VIRT imply CONFIG_CMD_SBI. The sbi command provides detailed information about the SBI. It is useful to test the discovery of extensions. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Heinrich Schuchardt authored
Let the sbi command display: * machine vendor ID * machine architecture ID * machine implementation ID With this patch the output for the HiFive Unmatched looks like => sbi SBI 0.3 OpenSBI 0.9 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 20181004 Extensions: sbi_set_timer sbi_console_putchar sbi_console_getchar sbi_clear_ipi sbi_send_ipi sbi_remote_fence_i sbi_remote_sfence_vma sbi_remote_sfence_vma_asid sbi_shutdown SBI Base Functionality Timer Extension IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Signed-off-by:Sean Anderson <seanga2@gmail.com>
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Heinrich Schuchardt authored
Provide library functions to read: * machine vendor ID * machine architecture ID * machine implementation ID Signed-off-by:
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Heinrich Schuchardt authored
Version 1.0-rc3 of the RISC-V Supervisor Binary Interface Specification has added the Performance Monitoring Unit Extension. The sbi command should be able to detect it. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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- Apr 05, 2022
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The tps65217 PMIC driver is used with am335x SoC based designs. It is used in the SPL (MLO) as well, so the DM conversion only is for u-boot proper. This driver only allows simple reading/writing/dumping of the content of its registers and requires the DM_I2C for proper operation. Signed-off-by:
Lukasz Majewski <lukma@denx.de> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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Up till now the CONFIG_POWER_TPS65217 has been defined in several header files for am335x SoC. This patch renames it to CONFIG_PMIC_TPS65217, which better reflects the role of this IC circuit. Moreover, new CONFIG_PMIC_TPS65217 has been introduced in Kconfig to be used with boards, which both support DM_PMIC and DM_I2C. Signed-off-by:
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Tom Rini authored
- Updates for exynos78x0 and TI K3 platforms
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Tom Rini authored
Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
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T Karthik Reddy authored
Add support for SGMII dynamic configuration which will takes care of configuring SGMII in the GEM secure (GEM_CLK_CTRL) configuration register. Signed-off-by:
T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/a8915186e44015959978d080a31de652f544cd4a.1648631275.git.michal.simek@xilinx.com
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T Karthik Reddy authored
Add zynqmp_pm_set_gem_config() api to configure GEM secure registers. Signed-off-by:
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T Karthik Reddy authored
In current slg7xl45106 gpio driver xlate() function we are not updating gpio flags from DT. Read the given flag from DT and update the gpio desc flags variable with required gpio direction state. Signed-off-by:
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T Karthik Reddy authored
As we are not reading the PHY address in case of CONFIG_ETH_PHY in plat function, phy address always prints as -1. So move the ethernet info print statement to probe function, to display proper phy address. Signed-off-by:
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T Karthik Reddy authored
If DM_ETH_PHY config is enabled PHY gpio reset is taken care by the eth-phy-uclass driver, so use the PHY gpio reset functionality from ethernet_id file when this config is disabled to reset the PHY. Use debug() print instead of dev_err() to avoid warning incase if phy-id compatible string is not present. Signed-off-by:
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Michal Simek authored
CONFIG_ETH_PHY enables support to utilize generic ethernet phy framework. Though if ethernet PHY node is in other ethernet node, it will use shared MDIO to access the PHY of other ethernet. Signed-off-by:
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Michal Simek authored
There are some new power domain IDs which are used in Linux kernel that's why add them here too. Signed-off-by:
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Michal Simek authored
Add ID code for 1eg device. Signed-off-by:
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T Karthik Reddy authored
While creating a phy device using phy_device_create(), we need to provide a valid phyaddr instead of 0 causing phy address being registered as 0 with mdio bus and shows mdio phy list as below ZynqMP> mdio list eth0: 0 - TI DP83867 <--> ethernet@ff0b0000 eth1: 0 - TI DP83867 <--> ethernet@ff0c0000 Also PHY soft reset is being requested on 0 instead of valid address causing "PHY reset timed out" error. So add phyaddr argument to phy_connect_phy_id() and to its prototype to create phy device with valid phyaddress. Fixes: a744a284 ("net: phy: Add support for ethernet-phy-id with gpio reset") Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Link: https://lore.kernel.org/r/fe35fddb9faa5af577ffdfabaec6879c935a30f8.1648562755.git.michal.simek@xilinx.com -
Michal Simek authored
Add support for getting rate for DP audio and video clocks. Signed-off-by:
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https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini authored
A big part is the DM pinctrl driver, which allows us to get rid of quite some custom pinmux code and make the whole port much more robust. Many thanks to Samuel for that nice contribution! There are some more or less cosmetic warnings about missing clocks right now, I will send the trivial fixes for that later. Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0 (secure images) support. Both features are unused at the moment, but I have an always-secure board that will use that once the DT lands in the kernel. On top of those big things we have some smaller fixes, improving the I2C DM support, fixing some H6/H616 early clock setup and improving the eMMC boot partition support. The gitlab CI completed successfully, including the build test for all 161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100 board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
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Michal Simek authored
Recently big Linux kernels can have more then 60MB that's why increase this limit to also cover these large kernels. Signed-off-by:
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- Apr 04, 2022
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André Przywara authored
Now that the SPL can safely detect whether it was loaded from an eMMC boot partition or the normal user data partition, let's enable this feature on some boards that feature eMMC storage. That covers the boards where I could test this on, and allows the same build to be written to an SD card, eMMC user partition, eMMC boot partition, or into SPI NOR flash. Signed-off-by:Andre Przywara <andre.przywara@arm.com>
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André Przywara authored
When the Allwinner BROM loads the SPL from an eMMC boot partition, it sets the boot source byte to the same value as when booting from the user data partition. This prevents us from determining the boot source to load U-Boot proper from the proper partition for sure. The generic SPL MMC code already looks at the enabled boot partition number, to load U-Boot proper from the same partition, but this fails if there is nothing bootable in this partition, as the BROM then silently falls back to the user data partition, which the SPL misses. To learn about the actual boot source anyway, we repeat the algorithm the BROM used to select the boot partition in the first place: - Test EXT_CSD[179] to check if an eMMC boot partition is enabled. - Test EXT_CSD[177] to check for valid MMC interface settings. - Check if BOOT_ACK is enabled. - Check the beginning of the first sector for a valid eGON signature. - Load the whole SPL. - Recalculate the checksum to verify the SPL is valid. If one of those steps fails, we bail out and continue loading from the user data partition. Otherwise we load from the selected boot partition. Since the boot source is needed twice in the boot process, we cache the result of this test to avoid doing this costly test multiple times. This allows the very same image file to be put onto an SD card, into the eMMC user data partition or into the eMMC boot partition, and safely loads the whole of U-Boot from there. Signed-off-by: -
Signed-off-by:Christian Gmeiner <christian.gmeiner@gmail.com>
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Makes it possible to use 16-bit DDR memory. Signed-off-by:
Dominic Rath <rath@ibv-augsburg.net> Signed-off-by:
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Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed to calculate the size of DDR that is available. Signed-off-by:Dave Gerlach <d-gerlach@ti.com>
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Add 'ss_cfg' memory region for memorycontroller node which is required to enable ECC. Signed-off-by: -
Call into k3-ddrss driver to fixup device tree and resize the available amount of DDR if ECC is enabled. A second fixup is required from A53 SPL to take the fixup as done from R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes this to the OS. Signed-off-by: -
Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: -
The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by:
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