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    • Tom Rini's avatar
      Merge branch '2021-09-17-TI-platform-updates' · d0b8c9a2
      Tom Rini authored 
      - Assorted bugfixes for TI platforms
      d0b8c9a2
    • Nishanth Menon's avatar
      arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup · ee91d465
      Nishanth Menon authored and Tom Rini's avatar Tom Rini committed 
      
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.

However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.

As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.

To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.

We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      ee91d465
    • Roger Quadros's avatar
      arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge · 6887f8e0
      Roger Quadros authored and Tom Rini's avatar Tom Rini committed 
      
NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).

This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.

This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.

Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Acked-by: default avatarAndrew F. Davis <afd@ti.com>
Acked-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: default avatarBenoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: default avatarNishanth <Menon&lt;nm@ti.com>
      6887f8e0
    • Suman Anna's avatar
      clk: ti: k3: Update driver to account for divider flags · cfd50dfb
      Suman Anna authored and Tom Rini's avatar Tom Rini committed 
      
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.

Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      cfd50dfb
    • Dave Gerlach's avatar
      clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write · d3c56e2a
      Dave Gerlach authored and Tom Rini's avatar Tom Rini committed 
      
There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.

Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.

Fixes: 0aa2930c ("clk: add support for TI K3 SoC PLL")
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      d3c56e2a
    • Dave Gerlach's avatar
      arm: mach-k3: Add note to auto-generated files · ae8d3d23
      Dave Gerlach authored and Tom Rini's avatar Tom Rini committed 
      
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.

Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.

Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      ae8d3d23
    • Suman Anna's avatar
      arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks · 326c03b5
      Suman Anna authored and Tom Rini's avatar Tom Rini committed 
      
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729ea ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      326c03b5
    • Suman Anna's avatar
      arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks · f1a815d0
      Suman Anna authored and Tom Rini's avatar Tom Rini committed 
      
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729ea ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
      f1a815d0

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