- Apr 07, 2017
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Recently some sunxi related code was moved to arch/arm/mach-sunxi, but the MAINTAINERS entry was not updated to reflect this. Add this, and the board level boards/sunxi directory to our entry. While at it, also update its status, to reflect the current active maintainership. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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The Sunchip CX-A99 is a board used in some media players. It features: An Allwinner A80 ARM SoC (4 * Cortex-A7 + 4 * Cortex-A15 cores) 2 GiB or 4 GiB DDR3 DRAM AXP808 PMIC 16 GB or 32 GB eMMC SDIO Wifi/Bluetooth/FM module SD card slot 1 USB 3.0 connector 2 USB 2.0 connectors SATA connector UART connector (internally) for serial console Ethernet connector (10/100/1000 Mbit/s) HDMI connector Composite video and analog audio connector S/PDIF connector IR remote control receiver This patch adds a defconfig for the board. The DRAM settings are as found in the vendor sys_config.fex file. It has a preliminary device tree for use until a device tree is accepted upstream, after which it can be replaced by the upstream version. Signed-off-by:
Rask Ingemann Lambertsen <rask@formelder.dk> [squash commits, and edited new meanful commit message] Signed-off-by:
Jagan Teki <jagan@openedev.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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commit 56b0730157f70dc23d6caff9e7ceb8b377b96b9f upstream. On the A80, mmc1 is available on pingroup G. Designs mostly use this to connect to an SDIO WiFi chip. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Rask Ingemann Lambertsen <rask@formelder.dk> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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The CHIP Pro is a SoM that features the GR8 SIP, an AXP209, a BT/WiFi chip and a 512MiB SLC NAND. This it's an SLC NAND, it doesn't suffer the same drawbacks than found on the MLC NANDs, and we can enable it right away. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Those DT will be part of 4.10, sync them so we can have our own config. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Jagan Teki <jagan@openedev.com>
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Introduce a new sunxi-spl-with-ecc.bin image with already the right header, ECC, randomizer and padding for the BROM to be able to read it. It needs to be flashed using a raw access to the NAND so that the controller doesn't change a thing to it, since we already have all the right parameters. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by:
Heiko Schocher <hs@denx.de>
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The SPL image needs to be built with a different ECC configuration than the U-Boot binary. Add Kconfig options with defaults to provide a value that should work for anyone, but is still configurable if needs be. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Scott Wood <oss@buserror.net> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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In order for the user to be able to see and modify them, add those variables to the default environment. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Enable the NAND and UBI support in the configuration header so that we can (finally) use it. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Jagan Teki <jagan@openedev.com>
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The default U-Boot offset for the Allwinner SoCs was set to 32kB. This was probably to try to maintain some compatibility with the current image that we build for the MMC where the U-Boot binary is also located at a 32kB offset. However, this causes a number of issues. The first one is that it prevents us from using a backup SPL entirely, which is troublesome in case where the first would be corrupt (especially on MLC which have a higher number of bitflips). We also cannot use the original MMC image on the NAND, because we need to prepare the SPL image to include the ECCs and randomizer settings, which reduces the interest of setting it at that particular offset. It also prevents us from upgrading and flashing the U-Boot and SPLs independantly, since it's very likely that it will fall in the same erase block. Since that default wasn't used by any board, change it for 8MB, which will be in an erase block of its own, all the erase blocks being multiple of two. The highest erase block size we encountered is 4MB, which means that in this particular setup, the first and second erase blocks will be for the SPL and its backup, and the third for U-Boot. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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We'll need that symbol so that the default offset are defined Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Sometime we need to enable advanced suboptions of the nand command set. Expose these suboptions in Kconfig. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Create a new Kconfig entry to allow CMD_UBIFS selection from Kconfig and add an hidden LZO option that can be selected by CMD_UBIFS. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Jagan Teki <jagan@openedev.com>
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Expose the RBTREE feature through Kconfig and select this option from the MTD_UBI option. Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Jagan Teki <jagan@openedev.com> [Rebased on master] Signed-off-by:
Jagan Teki <jagan@openedev.com>
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CMD_MTDPARTS is something the user might or might not want to select, and might depends on (or be selected by) other options too. This is even truer for the MTDIDS_DEFAULT and MTDPARTS_DEFAULT options that might change from one board to another, or from one user to the other, depending on what it expects and what storage devices are available. In order to ease that configuration, add those options to Kconfig. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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The environment location is something that might change per board (depending on what storage options are availaible there) or depending on the user choice (when we have several options). Instead of hardcoding it in our configuration header, create a Kconfig choice with the options we use for now, and the symbols that depend on it. Once done, also remove the irrelevant sunxi defines. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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This program generates raw SPL images that can be flashed on the NAND with the ECC and randomizer properly set up. This has been copied (and tweaked to find the right headers) from the sunxi-tools (https://github.com/linux-sunxi/sunxi-tools ) upstream repository, commit 1c3a6ca5. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Reviewed-by:
Hans de Goede <hdegoede@redhat.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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We will need the bch functions in the tool to generate the SPL images for the Allwinner SoCs. Do the needed adjustments so that we can use it on the host. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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When trying to autodetect the ECC and randomization configurations, the driver starts with a randomization disabled and no seeds. In this case, the number of seeds is obviously 0, and the randomize boolean is set to false. However, the logic that retrieves the seed for a given page offset will blindly use the number of seeds, without testing if the randomization is enabled, basically doing a modulo by 0. As it turns out, the libgcc in the common toolchain returns 0 here, which was our expected value in such a case, and why we would not detect it. However, U-Boot's libgcc will for some reason return from the function instead, resulting in an error to load the U-Boot binary in the SPL. Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by:
Scott Wood <oss@buserror.net> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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Add support for the NanoPi NEO Air H3 board from friendlyarm.com . This board contains WiFi, Bluetooth, 8GB eMMC storage and 512 MB DDR3 ram. Signed-off-by:
Jelle van der Waa <jelle@vdwaa.nl> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> [Rebase on master] Signed-off-by:
Jagan Teki <jagan@openedev.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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This ports the support for configuring a GPIO for resetting the Ethernet PHY (incl. such details as the reset polarity and pulse-length) from the Designware driver. X-AffectedPlatforms: A64-uQ7 Signed-off-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by:
Jagan Teki <jagan@openedev.com>
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git://git.denx.de/u-boot-sunxiTom Rini authored
trini: Disable CONFIG_SPL_USE_ARCH_MEMSET on orangepi_2 Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Apr 05, 2017
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Add separate enable/disable controls for driver-model serial. While this is generally enabled in SPL it may not be in TPL, since serial output can be obtained with the debug UART with minimal code size. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Since TPL often needs to be very very small it may not make sense to enable driver model. Add an option for this. This changes brings the 'rock' board under the TPL limit with gcc 4.9. Signed-off-by:
Simon Glass <sjg@chromium.org>
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At present we have SPL_ which can be used in Makefiles to select between normal and SPL CONFIGs like this: obj-$(CONFIG_$(SPL_)DM) += core/ When TPL is being built, SPL_ has the value 'SPL' which is generally a good idea since they tend to follow each other. But in extreme situations we may want to distinugish between SPL and TPL. For example we may not want to enable CONFIG_DM with TPL. Add a new SPL_TPL_ variable which is set to either empty (for U-Boot proper), 'SPL' or 'TPL'. This may prove useful with TPL-specific options. Signed-off-by:
Simon Glass <sjg@chromium.org>
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These includes don't seem to be needed now. Drop them. Reserve the mp.h header for PowerPC for now. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Stefan Roese <sr@denx.de> Reviewed-by:
York Sun <york.sun@nxp.com>
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This header file is used by three archs. It could be used by all of them since relocation is a common function. Move it into a generic file. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This header file is used by two archs. It could be used by all of them since it allows the cache to be on during relocation. Move it into a generic file. Signed-off-by:
Simon Glass <sjg@chromium.org>
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We don't need this PPC-specific function in generic code. Move it to the powerpc directory. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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This is to keep the header file order consistent. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
York Sun <york.sun@nxp.com>
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Drop headers which are not used or needed in this file. The compiler.h header is included by common.h. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
York Sun <york.sun@nxp.com>
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This is an weak function present on all archs so we should have it in the common header file. Remove it from arch-specific headers and add a function comment. Signed-off-by:
Simon Glass <sjg@chromium.org>
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By making dram_init_banksize() return an error code we can drop the wrapper. Adjust this and clean up all implementations. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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This is never defined when building this file, so drop it. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
York Sun <york.sun@nxp.com>
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Move the ugly #ifdefs inside the reserve_video() function so we can collect all this init into one place. Signed-off-by:
Simon Glass <sjg@chromium.org>
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The arch-specific details of the cache being off are best handled inside the reserve_mmu(). This cleans up the init sequence a little. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
York Sun <york.sun@nxp.com>
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CONFIG_ALT_LB_ADDR is really a detail of how this logbuffer is allocated rather than whether to do it at all. So move the #ifdef into the function. Signed-off-by:
Simon Glass <sjg@chromium.org>
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All archs put U-Boot at the bottom of the relocated region. Xtensa does not, but perhaps not for any good reason. Adjust it to see if things still work OK. Signed-off-by:
Simon Glass <sjg@chromium.org>
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At present we cannot use this function as an init sequence call without a wrapper, since it returns the RAM size. Adjust it to set the RAM size in global_data instead, and return 0 on success. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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It looks like only cm5200 and tqm8xx use this feature, so we don't really need it in generic code. Drop it and have the users access gd->board_type directly. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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