- Apr 02, 2024
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The only call site of dwc3_uboot_handle_interrupt() is the dm_usb_gadget_handle_interrupts(), fold the former into the later. This makes dwc3_uboot_handle_interrupt() unavailable to be called from board code as well. Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by:
Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # vim3 Link: https://lore.kernel.org/r/20240317044357.547037-2-marek.vasut+renesas@mailbox.org Signed-off-by:
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The dm_usb_gadget_handle_interrupts() has no place in board code. Move this into DWC3 driver. The OMAP implementation is special, add new weak dwc3_uboot_interrupt_status() function to decide whether DWC3 interrupt handling should be called, and override it in OMAP DWC3 code, to repair the special OMAP interrupt handling code until OMAP gets switched over to DM UDC proper. Signed-off-by:
Caleb Connolly <caleb.connolly@linaro.org> Reviewed-by:
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- Mar 22, 2024
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The priv struct was wrong in dump_boot_mappings(). Causing errors when compiling with -DDEBUG. Fix this. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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UFS storage often uses a 4096-byte sector size, add support for dynamic sector sizes based loosely on the Linux implementation. Support for dynamic sector sizes changes the types used in some divisions, resulting in the compiler attempting to use libgcc helpers (__aeabi_ldivmod). Replace these divisions with calls to lldiv() to handle this correctly. Reviewed-by:
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To actually use the gadget the peripheral driver must be probed and we must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always fail to find a UDC on DT platforms. Reviewed-by:
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- Mar 21, 2024
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The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented the missing initialisation for host and gadget mode. Reviewed-by:
Marek Vasut <marex@denx.de> Reviewed-by:
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- Mar 20, 2024
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Tom Rini authored
- TI J7200 updates, GIC-600 support, 2 more tests, fix parsing ccsidr_el1 register in some cases, prepare for allowing remoteproc to use fs_loader and make the binary_size_check rule not require 'bc'.
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- Mar 19, 2024
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Add a test for reset commands which performs resetting of CPU, It does COLD reset by default and WARM reset with -w option. Signed-off-by:Love Kumar <love.kumar@amd.com>
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Add test case for saveenv command in non-JTAG bootmode which saves the u-boot environment variables in persistent storage. Signed-off-by: -
The error message "bc: command not found" is easily missed since the build continues. bc is not a part of coreutils or base-devel. POSIX sh can also do the calculation. Signed-off-by:
Leon M. Busch-George <leon@georgemail.eu> Reviewed-by:
Dragan Simic <dsimic@manjaro.org>
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Current Cache Size ID Register (ccsidr_el1) has two "flavors" depending on whether FEAT_CCIDX is implemented or not. When FEAT_CCIDX is implemented Associativity parameter is coded on bits [23:3] and NumSets parameter on bits [55:32]. When FEAT_CCIDX is not implemented then Associativity parameter is coded on bits [12:3] and NumSets parameter on bits [27:13]. Current U-Boot code does not check whether FEAT_CCIDX is implemented and always parses ccsidr_el1 as if FEAT_CCIDX was not implemented. This is of course wrong on systems where FEAT_CCIDX is implemented. This patch fixes that problems and tests whether FEAT_CCIDX is implemented or not and accordingly parses the ccsidr_el1 register. Signed-off-by:Lukasz Wiecaszek <lukasz.wiecaszek@gmail.com>
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Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Power on the redistributor and wait until the power on state is reflected by checking the bit GICR_PWRR.RDPD == 0. While running U-Boot in EL3 without enabling this register, GICR_WAKER.ChildrenAsleep bit is not getting cleared and loops infinitely. This register(GICR_PWRR) must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. ARM GIC-600 IP complies with ARM GICv3 architecture. Enable this config if GIC-600 IP present. Signed-off-by:Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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Corrects the ti,sci property to point to dm_tifs node for proper functioning of mcu_ringacc and mcu_udmap. Fixes: df73e791 ("arm: dts: j7200: dts sync with Linux 6.6-rc1") Signed-off-by:
Aniket Limaye <a-limaye@ti.com>
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Correcting the clock-frequency property of the mcu_timer0 node Fixes: df73e791 ("arm: dts: j7200: dts sync with Linux 6.6-rc1") Signed-off-by:
Udit Kumar <u-kumar1@ti.com>
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- Add the missing bootph-all property in the flash subnode for ospi - Add the missing overrides for the ospi node in the r5 devicetree Signed-off-by:
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Add the necessary configs required for OSPI functionality. Also update the ospi flash partition offsets as per the devicetree. Signed-off-by:
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load_firmware() API calls fs-loader APIs and checks for CONFIG_FS_LOADER before calling those APIs. The if check only checks for CONFIG_FS_LOADER but not for CONFIG_SPL_FS_LOADER. When CONFIG_FS_LOADER is enabled, load_firmware() API calls fs-loader APIs but this is done at SPL stage and at this time FS_LOADER is not built yet as a result we see below build error. AR spl/boot/built-in.o LD spl/u-boot-spl arm-none-linux-gnueabihf-ld.bfd: arch/arm/mach-k3/common.o: in function `load_firmware': /home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:184: undefined reference to `get_fs_loader' arm-none-linux-gnueabihf-ld.bfd: /home/danish/workspace/u-boot/arch/arm/mach-k3/common.c:185: undefined reference to `request_firmware_into_buf' make[2]: *** [/home/danish/workspace/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 make[1]: *** [/home/danish/workspace/u-boot/Makefile:2055: spl/u-boot-spl] Error 2 make[1]: Leaving directory '/home/danish/uboot_images/am64x/r5' make: *** [Makefile:177: sub-make] Error 2 Fix this by modifying the if check to CONFIG_IS_ENABLED(FS_LOADER) instead of IS_ENABLED(CONFIG_FS_LOADER) as the former will check for the appropriate config option (CONFIG_SPL_FS_LOADER / CONFIG_FS_LOADER) based on the build stage. Signed-off-by:
MD Danish Anwar <danishanwar@ti.com> Acked-by:
Ravi Gunasekaran <r-gunasekaran@ti.com>
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Tom Rini authored
Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next - A new driver in the misc to register setting from device tree. This also provides user a clean interface and all register settings are centralized in one place, device tree. - Enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Build-tested on SoC64 boards, boot tested on some of them.
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- Mar 18, 2024
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This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by:
Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by:
Tien Fong Chee <tien.fong.chee@intel.com>
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Add socfpga_dtreg driver enablement for Intel SoCFPGA. Signed-off-by:
Wan Yee Lau <wan.yee.lau@intel.com> Reviewed-by:
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Tom Rini authored
Merge tag 'u-boot-imx-next-20240317' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/19975 - Select polling-rate from cpu-thermal devicetree node on imx_tmu. - Re-organize the U-Boot environment and add RAUC logic for phycore_imx8mp. - Enable watchdog on colibri-imx7. - Move imx8mm-venice to use OF_UPSTREAM.
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- Mar 17, 2024
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Tim Harvey authored
Move to imx8m{m,n,p}-venice to OF_UPSTREAM: - replace the non-upstream generic imx8m{m,n,p}-venice dt with one of the dt's from the OF_LIST - handle the fact that dtbs now have a 'freescale/' prefix - imply OF_UPSTREAM - remove rudundant files from arch/arm/dts leaving only the *-u-boot.dtsi files Signed-off-by:Tim Harvey <tharvey@gateworks.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Reviewed-by:
Sumit Garg <sumit.garg@linaro.org>
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Leonard Anderweit authored
Add RAUC boot logic to the environment. This is the first board to utilize this environment. Signed-off-by:
Leonard Anderweit <l.anderweit@phytec.de> Tested-by:
Teresa Remmet <t.remmet@phytec.de>
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Leonard Anderweit authored
Add logic for booting systems with the RAUC update mechanism. This can be reused by other phytec boards. Signed-off-by:
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Leonard Anderweit authored
Add support for the redundant environment. Signed-off-by:
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Leonard Anderweit authored
Move the default bootcmd from the defconfig to the board environment. No change in functionality. Signed-off-by:
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Leonard Anderweit authored
Move the environment into the board directory and convert it from a C header to a text file. Sort the variables alphabetically. No functional changes. Signed-off-by:
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Benjamin Hahn authored
The polling rate is already specified in some devicetrees, like imx8mp.dtsi for example, but was not selected so far. For the trippoints, the cpu-thermal node is used. Also get the polling rate from this node. Use the default of 5000ms if the polling rate should not be specified in the devicetree. NOTE: The polling rate from the devicetree will be used after this patch. In imx8*.dtsi devicetrees the polling delay is set to 2000ms for example. Signed-off-by:
Benjamin Hahn <B.Hahn@phytec.de> Reviewed-by:
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Parth Pancholi authored
Enable watchdog functionality for Toradex's Colibri iMX7 (NAND/EMMC) modules. Signed-off-by:Parth Pancholi <parth.pancholi@toradex.com>
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- Mar 15, 2024
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Tom Rini authored
Merge tag 'u-boot-rockchip-20240315' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next Please pull the updates for rockchip platform: - Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC, Toybrick TB-RK3588X; rk3588s Cool Pi 4B; rk3566 Pine64 PineTab2; - Add saradc v2 support; - Add PMIC RK806 support; - rk3588 disable force_jtag by default; - Migrate to use IO-domain driver for all boards; - Use common bss and stack addresses for rk33xx and rk35xx boards; - Other updates for driver, config and dts;
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Tom Rini authored
This moves us to our latest container image, which is now based on the current "Jammy" tag. Signed-off-by:Tom Rini <trini@konsulko.com>
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- Mar 14, 2024
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Tom Rini authored
In order to support the reset pytest on QEMU on m68k platforms we need to grab this change from upstream. Signed-off-by: -
Tom Rini authored
Currently, llvm-17 is the stable release. Update our container and CI to fetch and use that. Signed-off-by: -
Bootgen is used in a binman test. The test is skipped without the binary. Signed-off-by:Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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Fiptool is used in a binman test. The test is skipped without the binary. Signed-off-by: -
ADC support is implied by the Rockchip arch Kconfig but that means it should be possible to disable ADC support and still be able to build. However the weak implementation of rockchip_dnl_key_pressed() currently blindly use functions from the ADC subsystem which do not exist when ADC is not enabled, failing the build. Therefore, let's encapsulate this logic with a check on the ADC symbol being selected. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com> Signed-off-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com>
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The BUTTON_ADC symbol guards the compilation of button-adc driver whose name very well makes it explicit that it requires ADC support to be enabled. Fix build issue of button-adc driver when ADC support isn't enabled by making sure it cannot be built without ADC support. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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The ADC controller drivers are obviously all depending on ADC symbol being selected. While they don't seem to fail to build without, they won't be useful without that symbol selected, so let's make sure the options aren't shown in menuconfig when ADC isn't selected. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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The SARADC is used on Jaguar for multiple things: - channel 0 is used (at runtime) as a BIOS button, - channel 2 is exposed on the Mezzanine connector for customer specific logic, - channel 5 and 6 are used for identification, Since the SARADC requires a vref-supply provided by the RK806 PMIC, its support and the support for its regulators are also enabled. The button, adc, pmic and regulator commands are also enabled for CLI use in U-Boot for debugging and scripting purposes. The RK806 PMIC on Jaguar being routed on the SPI bus, let's enable Rockchip SPI controller driver. Finally, the SARADC channel 1 on Jaguar is hardwired so will never change in the lifetime of a unit, for that reason, disable the Rockchip Download Mode check by setting ROCKCHIP_BOOT_MODE_REG symbol to 0. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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SPL_PMIC_RK8XX and PMIC_RK8XX both share the same prompt making it difficult to know at first glance in menuconfig what's for what, let's fix this by adding "in SPL" at the end of the prompt for the SPL symbol. Cc: Quentin Schulz <foss+uboot@0leil.net> Reviewed-by:
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