• Dave Gerlach's avatar
    clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write · d3c56e2a
    Dave Gerlach authored and Tom Rini's avatar Tom Rini committed
    There are three different divider values in the DIV_CTRL register
    controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
    function writes the entire register when programming plld, even though
    plld only resides in the lower 6 bits.
    
    Change the plld programming to read-modify-write to only affect the
    relevant bits for plld and to preserve the other two divider values
    present in the upper 16 bits, otherwise they will always get set to zero
    when programming plld.
    
    Fixes: 0aa2930c
    
     ("clk: add support for TI K3 SoC PLL")
    Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
    d3c56e2a
clk-k3-pll.c 6.75 KB