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    • Tom Rini's avatar
      Merge tag 'u-boot-stm32-20230816' of https://source.denx.de/u-boot/custodians/u-boot-stm · 375fea81
      Tom Rini authored
      DHSOM: Power cycle Buck3 in reset
      DHCOM: Switch DWMAC RMII clock to MCO2
      stm32f746: fix display pinmux
      stm32mp: psci: Inhibit PDDS because CSTBYDIS is set
      stm32mp1: DT alignment with v6.4
      stm32mp1: add splashscreen with STMicroelectronics logo
      stm32mp1: clk: remove error for disabled clock in stm32mp1_clk_get_parent
      serial: stm32: Extend TC timeout
      375fea81
    • Valentin Caron's avatar
      serial: stm32: extend TC timeout · 9e8cbea1
      Valentin Caron authored and Patrice Chotard's avatar Patrice Chotard committed
      
      Waiting 150us TC bit couldn't be enough.
      
      If TFA lets 16 bits in USART fifo, we has to wait 16 times 87 us (time
      of 10 bits (1 byte in most use cases) at a baud rate of 115200).
      
      Fixes: b4dbc5d6 ("serial: stm32: Wait TC bit before performing initialization")
      
      Signed-off-by: default avatarValentin Caron <valentin.caron@foss.st.com>
      Signed-off-by: Patrice Chotard's avatarPatrice Chotard <patrice.chotard@foss.st.com>
      9e8cbea1
    • Marek Vasut's avatar
      ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM · c9678850
      Marek Vasut authored and Patrice Chotard's avatar Patrice Chotard committed
      
      The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
      block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
      pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
      internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
      all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
      the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
      using external pad-to-pad connection.
      
      Option (1) has two downsides. ETHCK_K is supplied directly from either
      PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
      since the same PLL output is also used to supply SDMMC blocks, the
      performance of SD and eMMC access is affected. The second downside is
      that using this option, the EMI of the SoM is higher.
      
      Option (2) solves both of those problems, so implement it here. In this
      case, the PLL4_P is no longer limited and can be operated faster, at
      100 MHz, which improves SDMMC performance (read performance is improved
      from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
      count=1). The EMI interference also decreases.
      
      Ported from Linux kernel commit
      73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Reviewed-by: Patrice Chotard's avatarPatrice Chotard <patrice.chotard@foss.st.com>
      c9678850
    • Patrick Delaunay's avatar
      board: stm32mp1: add splash screen with stmicroelectronics logo · 284b08fb
      Patrick Delaunay authored and Patrice Chotard's avatar Patrice Chotard committed
      
      Display the STMicroelectronics logo with features VIDEO_LOGO and
      SPLASH_SCREEN on STMicroelectronics boards.
      
      With CONFIG_SYS_VENDOR = "st", the logo st.bmp is selected, loaded at the
      address indicated by splashimage and centered with "splashpos=m,m".
      
      Signed-off-by: Patrick Delaunay's avatarPatrick Delaunay <patrick.delaunay@foss.st.com>
      Reviewed-by: Patrice Chotard's avatarPatrice Chotard <patrice.chotard@foss.st.com>
      284b08fb
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