- Nov 02, 2024
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Simon Glass authored
This should say 'cast' rather than 'case', so fix it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This is mostly hidden in the background, but it is sometimes useful to look at it. Add a function to allow this. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This command has a few small features, so document it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Ise the new U_BOOT_CMD_WITH_SUBCMDS() macro instead of writing the code out manually. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Mark bloblist tests with this flag so that other tests which use bloblist remain unaffected. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Tests which create a new bloblist overwrite the existing one in sandbox. Provide a flag for tests to declare this behaviour. Save and restore the bloblist pointer so that other tests remain unaffected. Note that when sandbox is running normally, the bloblist has been relocated to high in memory. The existing bloblist tests create a new bloblist low in memory, so they do not conflict. Correct a build error on coreboot by using accessors for gd->bloblist: Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
In some core test code, no existing categories make sense. Add a new one for testing. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Coreboot provides the CMOS layout in the tables it passes to U-Boot. Use that to build an editor for the CMOS settings. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Coreboot tables provide information about the CMOS-RAM checksum. Add a command which can check and update this. With this it is possible to adjust CMOS-RAM settings and tidy up the checksum afterwards. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Enable cedit support along with required options and a simple style. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Update the cbsysinfo command to show the contents of the CMOS option table. While we are here, add some example output for this command, along with mention of what the unimplemented tags are. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add a simple test for this command, checking that coreboot has the required features. Signed-off-by:
Simon Glass <sjg@chromium.org>
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The timer counter on Rockchip SoCs may be reset in TF-A, this may cause the bootstage records to be printed out of order and with an incorrect elapsed time. Fix this by not sorting the bootstage records. Before on a Radxa ZERO 3W (RK3566) board: => bootstage report Timer summary in microseconds (12 records): Mark Elapsed Stage 0 0 reset 7,436 7,436 board_init_f 164,826 157,390 SPL 375,392 210,566 end phase 423,909 48,517 board_init_r 472,973 49,064 eth_common_init 476,848 3,875 main_loop 477,003 155 cli_loop Accumulated time: 7,181 of_live 14,739 dm_spl 15,029 dm_r 315,150 dm_f With this the records can be printed in chronological order when the counter is reset and SPL and board_init_r records show correct elapsed time. => bootstage report Timer summary in microseconds (12 records): Mark Elapsed Stage 0 0 reset 164,437 164,437 SPL 375,023 210,586 end phase 7,437 7,437 board_init_f 424,390 416,953 board_init_r 473,515 49,125 eth_common_init 477,402 3,887 main_loop 477,571 169 cli_loop Accumulated time: 14,734 dm_spl 315,646 dm_f 7,339 of_live 14,977 dm_r For the tested board external TPL and BROM take ~164 ms to initialize DRAM and load SPL, SPL take ~210ms to load images from FIT and U-Boot proper take ~477ms to reach cli prompt. Signed-off-by:
Jonas Karlman <jonas@kwiboo.se>
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Simon Glass authored
When the buffer address is not set, say so, rather than showing an address which looks very strange, on sandbox. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This should really use an address rather than the buffer. Update it in the command. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This test checks console output so should have the UTF_CONSOLE flag. Add it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
The mkimage call is done twice. Remove the duplicate. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
This function assumes that all tests in a suite are being run. This means that it can sometimes call dm_test_restore() when it should not. The impact of this is that it is not possible, for example, to run 'ut bootstd bootflow_cros' and then check the state of bootstd afterwards, since all devices are removed and recreated. Update the function to take account of any selected test, to avoid this problem. Add a comment for test_insert while we are here. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
In the bootflow tests the script bootmeth is bound with the name bootmeth_script whereas the others have a name without the bootmeth_ prefix. Adjust it to be the same. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Mattijs Korpershoek <mkorpershoek@baylibre.com>
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Simon Glass authored
All the uclass functions for finding a device end up creating a uclass if it doesn't exist. Add a function which instead returns NULL in this case. This is useful when in the 'unbind' path, since we don't want to undo any unbinding which has already happened. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add myself as maintainer of alist Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Unlike linked lists, it is inefficient to remove items from an alist, particularly if it is large. If most items need to be removed, then the time-complexity approaches O(n2). Provide a way to do this efficiently, by working through the alist once and copying elements down. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Sometimes it is useful to empty the list without de-allocating any of the memory used, e.g. when the list will be re-populated immediately afterwards. Add a new function for this. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add some macros which permit easy iteration through an alist, similar to those provided by the 'list' implementation. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add a new function which returns the next element after the one provided, if it exists in the list. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Add a better description for this macro. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Comment this macro so that it is clear how to use it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Update the function comment to note that this function can return NULL if it runs out of memory. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Oct 31, 2024
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Tom Rini authored
While we want to compile the SPI_STACKED_PARALLEL code everywhere we can, it must first be guarded with an #if for DM_SPI as not all cases where we have this code built, such as in SPL, will have the relevant DM_SPI option enabled. Fixes: 43423cdc ("mtd: spi-nor: Always build SPI_STACKED_PARALLEL code") Reviewed-by:
Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by:
Tom Rini <trini@konsulko.com>
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Tom Rini authored
Tom Rini <trini@konsulko.com> says: In the patch series "spi-nor: Add parallel and stacked memories support" a number of issues have since been raised about problems that now exist on a large number of previously working platforms. Marek Vasut has gone and identified a number of issues and this series is the starting point of attempting to address them and fix the problems with previously existing platforms. Link: https://patchwork.ozlabs.org/project/uboot/list/?series=429932&state=* Link: https://lore.kernel.org/r/20241026201741.171073-1-marek.vasut+renesas@mailbox.org
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Prevent the code gated by SPI_STACKED_PARALLEL from bitrot by using if (CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL)) around it. That way, it is always at least compiled. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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The SPI_ADVANCE description does not explain what the switch does. It does not have anything to do with any advanced functionality, it only gates off support for stacked and parallel SPI NORs. Rename the Kconfig symbol, update description, and move it right next to Xilinx hardware as it seems to be specific to this hardware. Make sure the symbol is also protected by if DM_SPI in Kconfig. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Rewrite the code to make it clear exactly where the SNOR_F_HAS_PARALLEL flag leads to *2 and /2 operation compared to regular code path. No functional change. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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The offset variable is set, but never used afterward. Fix indent. Fix predecrement without justification. Remove use of parenthesis where unnecessary. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Remove undocumented SST special case. This was added in commit 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") without any explanation in the commit message. Remove it. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Remove undocumented write_disable() call. This was added in commit 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") without any explanation in the commit message. Remove it. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Remove undocumented set_4byte() call. This was added in commit 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") without any explanation in the commit message. Remove it. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Remove undocumented spi_nor_wait_till_ready() call. This was added in commit 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") without any explanation in the commit message. Remove it. Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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Remove undocumented nor->addr_width == 3 test. This was added in commit 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") without any explanation in the commit message. Remove it. This also has a bad side-effect which breaks READ operation of every SPI NOR which does not use addr_width == 3, e.g. s25fs512s does not work at all. This is because if addr_width != 3, rem_bank_len is always 0, and if rem_bank_len is 0, then read_len is 0 and if read_len is 0, then the spi_nor_read() returns -EIO. Basic reproducer is as follows: " => sf probe ; sf read 0x50000000 0 0x10000 SF: Detected s25fs512s with page size 256 Bytes, erase size 256 KiB, total 64 MiB device 0 offset 0x0, size 0x10000 SF: 65536 bytes @ 0x0 Read: ERROR -5 " Fixes: 5d40b3d3 ("mtd: spi-nor: Add parallel and stacked memories support") Signed-off-by:
Marek Vasut <marek.vasut+renesas@mailbox.org>
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https://source.denx.de/u-boot/custodians/u-boot-efiTom Rini authored
Pull request efi-2025-01-rc2 Documentation: * include semihosting and K3 boards only once in table of contents * include file-system API into HTML docs * describe struct ext2_inode * update Python requirements UEFI: * mark local functions static * simplify efi_free_pages() * pass correct end address value to efi_dp_from_mem() * fix typos in HII test and eficonfig command
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