Xilinx changes for v2023.10-rc1 v2 axi_emac: - Change return value if RX packet is not ready cadence_qspi: - Enable flash reset for Versal NET dt: - Various DT syncups with Linux kernel - SOM - reserved pmufw memory location fpga: - Add load event mtd: - Add missing dependency for FLASH_CFI_MTD spi/nand: - Minor cleanup in Xilinx drivers versal-net: - Prioritize boot device in boot_targets - Wire mini ospi/qspi/emmc configurations watchdog: - Use new versal-wwdt property xilinx: - fix sparse warnings in various places ps7_init* - add missing headers - consolidate code around zynqmp_mmio_read/write - switch to amd.com email zynqmp_clk: - Add handling for gem rx/tsu clocks zynq_gem: - Configure mdio clock at run time zynq: - Enable fdt overlay support zynq_sdhci: - Call dll reset only for ZynqMP SOCs