- Oct 25, 2019
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Some configs are selected in Kconfig and is no longer needed in the defconfig files. Some configs (power domain, ram) are never used. Signed-off-by:Weijie Gao <weijie.gao@mediatek.com>
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Some drivers (clk, pinctrl, reset, ...) are necessary for reset of the system, they should be always selected. Signed-off-by: -
This patch changes baudrate table for all boards preparing for using mtk highspeed uart driver. Signed-off-by: -
This patch adds default eth pinctrl for all boards. There are two pinctrl nodes used for two scenarios: ephy_iot_mode - for IOT boards which have only one port (PHY0) ephy_router_mode - For routers which have more than one ports Reviewed-by:
Stefan Roese <sr@denx.de> Signed-off-by:
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This adds default pinctrl (dual SPI chip select) for gardena smart gateway Reviewed-by:
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This patch adds mmc related nodes for mt7628an.dtsi Signed-off-by: -
This patch adds a dts property cd-active-high for builtin-cd mode to make it configurable instead of using hardcoded active-low. Signed-off-by: -
This patch adds mmc support for MediaTek MT7620/MT7628 SoCs. Signed-off-by: -
This patch adds default p0led status and phy0 link polling for all boards. Reviewed-by:
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This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to prevent LAN devices from getting IP address from WAN. Signed-off-by: -
When received a packet with an invalid length recorded in rx descriptor, we should free this rx descriptor to allow us to continue to receive following packets. Without doing so, u-boot will stuck in a dead loop trying to process this invalid rx descriptor. This patch adds a call to mt7628_eth_free_pkt() after received an invalid packet length. Reviewed-by:
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The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port). Although in IOT mode only port0 is usable, the phy0 is still connected to the switch, not the ethernet gmac directly. This patch rewrites it and makes it optional. It can be turned on by adding mediatek,poll-link-phy = <?> explicitly into the eth node. By default the driver is switch mode with all 5 phy ports working without link detection. Signed-off-by: -
This patch removes hardcoded gpio settings as they have been replaced by pinctrl in dts, and also replaces regmap-based phy reset with a more generic reset controller. Reviewed-by:
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This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: -
This patch updates reset controller node for mt7628 Signed-off-by: -
This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: -
This patch adds default pinctrl for uart nodes Signed-off-by: -
This patch adds pinctrl node with default pin state for mt7628an.dtsi. Signed-off-by: -
This patch adds pinctrl support for mt7628, with a file for common pinmux functions and a file for mt7628 which has additional support for pinconf. Signed-off-by: -
Currently this driver uses a different way to implement the spi xfer, by modifying some fields of two registers, which is incompatible with the MTK's original SDK linux driver. This will cause the flash data being damaged by the SDK driver. This patch lets the mt7621_spi_set_cs() restore the original register fields after cs deactivated. Reviewed-by:
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The mt7621 spi controller supports continuous generic half-duplex spi transaction. There is no need to cache xfer data at all. To achieve this goal, the OPADDR register must be used as the first data to be sent. And follows the eight generic DIDO registers. But one thing different between OPADDR and DIDO registers is OPADDR has a reversed byte order. With this patch, any amount of data can be read/written in a single xfer function call. Reviewed-by:
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This patch lets the spi driver to use clock provided by the clk driver since the new clk-mt7628 driver provides accurate sys clock frequency. Signed-off-by: -
This patch adds clkctrl node for mt7628 and adds clocks property for some node. Signed-off-by: -
This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: -
All three UARTs of mt7628 are actually MediaTek's high-speed UARTs which support baudrate up to 921600. The high-speed UART is compatible with ns16550 when baudrate <= 115200. Add compatible string to dtsi file so u-boot can use it when serial_mtk driver is built in. Reviewed-by:
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The UART of MT7628 has fixed 40MHz input clock so there is no need to put clock-frequency in every dts files. Just put it into the common dtsi file. Reviewed-by:
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This patch adds non-DM version for mtk hsuart driver and makes it compatible with ns16550a driver in configuration. This is needed in SPL with CONFIG_SPL_DM disabled for reducing size. Signed-off-by: -
This patch adds codes to enable FIFO and disable flow control taken from ns16550 driver. Signed-off-by: -
The current brcmnand driver is based on 4.18 linux kernel which uses mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from old kernel which does not use this new API and expect nand_chip.ecc.layout structure to be set. This cause nand_scan_tail function running into a bug check if the device has a different oob size than the default ones. This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7 that supports the ecc layout struture and replaces the mtd_set_ooblayout method Signed-off-by:
William Zhang <william.zhang@broadcom.com> Reviewed-by:
Philippe Reynes <philippe.reynes@softathome.com>
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Fixes commit 344db3f3, which added missing bmips dtbs depending on their SoCs. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com>
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Signed-off-by: -
Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -
These are no longer needed. Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -
Signed-off-by: -
BCM63268 uses 4.0 HW nand controller, which is currently supported by brcmnand driver. Signed-off-by: -
BCM6362 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: -
BCM6328 uses old 2.2 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: -
BCM6368 uses old 2.1 HW nand controller, which isn't currently supported by brcmnand driver. Signed-off-by: -
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs. Signed-off-by:
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -
If configuration is set to skip low level init, automatic probe of L2 cache size is not performed and the size is set to 0. Flushing or invalidating the L2 cache will fail in this case. Add a static configuration (SYS_DCACHE_LINE_SIZE) with default set to 0. Signed-off-by:Ramon Fried <rfried.dev@gmail.com>
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