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Commit aba9f1af authored by Wolfgang Denk's avatar Wolfgang Denk
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Memory configuration changes for ZPC.1900 board 

- Fix SDRAM timing on both local bus and 60x bus
- Add support for second flash bank (SIMM)
- Change boot flash base
Patch by Yuli Barcohen, 05 Jun 2005
parent 5797b821
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CHANGELOG
+ 6
− 0
View file @ aba9f1af
......@@ -2,6 +2,12 @@
Changes since U-Boot 1.1.4:
======================================================================
* Memory configuration changes for ZPC.1900 board
- Fix SDRAM timing on both local bus and 60x bus
- Add support for second flash bank (SIMM)
- Change boot flash base
Patch by Yuli Barcohen, 05 Jun 2005
* Add support for Adder boards with 16MB SDRAM;
add support for second FEC on Adder87x board.
Patch by Yuli Barcohen, 05 Jun 2005
......
board/zpc1900/config.mk
+ 1
− 1
View file @ aba9f1af
......@@ -27,4 +27,4 @@
# ZPC.1900 board
#
TEXT_BASE = 0xFFE00000
TEXT_BASE = 0xFE000000
board/zpc1900/zpc1900.c
+ 14
− 18
View file @ aba9f1af
......@@ -2,7 +2,7 @@
* (C) Copyright 2001-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2003 Arabella Software Ltd.
* (C) Copyright 2003-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* See file CREDITS for list of people who contributed to this
......@@ -27,9 +27,6 @@
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <i2c.h>
#include <spd.h>
#include <miiphy.h>
/*
......@@ -167,8 +164,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
......@@ -231,11 +228,10 @@ long int initdram(int board_type)
vu_char *ramaddr;
uchar c = 0xFF;
long int msize = CFG_SDRAM_SIZE;
uint psdmr = CFG_PSDMR;
int i;
if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
......@@ -255,10 +251,10 @@ long int initdram(int board_type)
*/
if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
memctl->memc_lsrt = CFG_LSRT;
memctl->memc_or4 = 0xFFC01480;
memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
memctl->memc_or4 = CFG_LSDRAM_OR;
memctl->memc_br4 = CFG_LSDRAM_BR;
ramaddr = (vu_char *)CFG_LSDRAM_BASE;
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
......@@ -271,8 +267,8 @@ long int initdram(int board_type)
/* Initialise 60x bus SDRAM */
memctl->memc_psrt = CFG_PSRT;
memctl->memc_or2 = 0xFC0028C0;
memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
memctl->memc_or2 = CFG_PSDRAM_OR;
memctl->memc_br2 = CFG_PSDRAM_BR;
/*
* The mode data for Mode Register Write command must appear on
* the address lines during a mode-set cycle. It is driven by
......@@ -283,15 +279,15 @@ long int initdram(int board_type)
* length must be 4.
*/
ramaddr = (vu_char *)(CFG_SDRAM_BASE |
((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
*ramaddr = c;
memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN; /* Refresh enable */
*ramaddr = c;
#endif /* CFG_RAMBOOT */
......
include/configs/ZPC1900.h
+ 34
− 35
View file @ aba9f1af
/*
* Copyright (C) 2003-2004 Arabella Software Ltd.
* Copyright (C) 2003-2005 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
*
* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
......@@ -32,11 +32,7 @@
#define CPU_ID_STR "MPC8265"
#define CONFIG_CPM2 1 /* Has a CPM2 */
#undef DEBUG
#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE
/*
......@@ -113,7 +109,6 @@
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_DHCP \
| CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_MII \
| CFG_CMD_PING \
......@@ -154,31 +149,30 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
#define CFG_DEFAULT_IMMR 0x0F010000
#define CFG_IMMR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 64
#define CFG_FLSIMM_BASE 0xFC000000
#define CFG_LSDRAM_BASE 0xFE000000
#define CFG_IMMR 0xF0000000
#define CFG_LSDRAM_BASE 0xFC000000
#define CFG_FLASH_BASE 0xFE000000
#define CFG_BCSR 0xFEA00000
#define CFG_EEPROM 0xFEB00000
#define CFG_FLSIMM_BASE 0xFF000000
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
#define BCSR_PCI_MODE 0x01
......@@ -190,10 +184,10 @@
/* Hard reset configuration word */
#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10 |\
HRCW_MODCK_H0101 \
) /* 0x16828605 */
HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
HRCW_MODCK_H0111 \
) /* 0x16848207 */
/* No slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
......@@ -211,7 +205,7 @@
#define CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
......@@ -233,14 +227,14 @@
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
#define CFG_HID0_INIT (HID0_ICFI)
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
#define CFG_HID2 0
#define CFG_SIUMCR 0x42200000
#define CFG_SYPCR 0xFFFFFFC3
#define CFG_BCR 0x90400000
#define CFG_BCR 0x90000000
#define CFG_SCCR SCCR_DFBRG01
#define CFG_RMR RMR_CSRE
......@@ -248,18 +242,23 @@
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RCCR 0
#define CFG_PSDMR 0x014EB45A
#define CFG_PSRT 0x0C
#define CFG_LSDMR 0x008AB552
#define CFG_LSRT 0x0E
#define CFG_PSDMR /* 0x834DA43B */0x014DA43A
#define CFG_PSRT 0x0F/* 0x0C */
#define CFG_LSDMR 0x0085A562
#define CFG_LSRT 0x0F
#define CFG_MPTPR 0x4000
#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041
#define CFG_PSDRAM_OR 0xFC0028C0
#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861
#define CFG_LSDRAM_OR 0xFF803480
#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
#define CFG_OR0_PRELIM 0xFFE00856
#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
#define CFG_OR5_PRELIM 0xFFFF03F6
#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801
#define CFG_OR6_PRELIM 0xFE000856
#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801
#define CFG_OR6_PRELIM 0xFF000856
#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
#define CFG_OR7_PRELIM 0xFFFF83F6
......
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