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Commit dc77d0f9 authored by Ye Li's avatar Ye Li Committed by Stefano Babic
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imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock


The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan's avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarYe Li <ye.li@nxp.com>
Signed-off-by: Peng Fan's avatarPeng Fan <peng.fan@nxp.com>
parent 0f9b10aa
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