- Oct 05, 2024
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Tom Rini authored
Merge branch 'u-boot-nand-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash into next These are a number of assorted upstream Linux fixes to the BRCMNAND driver. This patch set lowers the hamming distance between the Linux and U-Boot drivers a bit as well, while we deviate quite a bit it is still possible to bring fixes over thanks to exercises like this. The patches pass the pipeline CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/22535
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Backport from the upstream Linux kernel commit c2cf7e25eb2a3c915a420fb8ceed8912add7f36c "mtd: rawnand: brcmnand: Add support for getting ecc setting from strap" Note: the upstream kernel introduces a new bool brcmnand_get_sector_size_1k() function because the int version in U-Boot has been removed in Linux. I kept the old int-returning version that is already in U-Boot as we depend on that in other code. BCMBCA broadband SoC based board design does not specify ecc setting in dts but rather use the SoC NAND strap info to obtain the ecc strength and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for this purpose and update driver to support this option. However these two options can not be used at the same time. Signed-off-by:
William Zhang <william.zhang@broadcom.com> Reviewed-by:
David Regan <dregan@broadcom.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20240301173308.226004-1-william.zhang@broadcom.com Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
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Backport of upstream Linux commit 8e7daa85641c9559c113f6b217bdc923397de77c "mtd: rawnand: brcmnand: Support write protection setting from dts" Augmented to also support the "write-protect" boolean property. The write protection feature is controlled by the module parameter wp_on with default set to enabled. But not all the board use this feature especially in BCMBCA broadband board. And module parameter is not sufficient as different board can have different option. Add a device tree property and allow this feature to be configured through the board dts on per board basis. Signed-off-by:
Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by:
Kamal Dasu <kamal.dasu@broadcom.com> Reviewed-by:
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This is a port of the read data bus interface from the Linux brcmnand driver, commit 546e425991205f59281e160a0d0daed47b7ca9b3 "mtd: rawnand: brcmnand: Add BCMBCA read data bus interface" This is needed for the BCMBCA RAW NAND driver. Signed-off-by:
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Backport from upstream Linux commit 60177390fa061c62d156f4a546e3efd90df3c183 "mtd: rawnand: brcmnand: Fix mtd oobsize" brcmnand controller can only access the flash spare area up to certain bytes based on the ECC level. It can be less than the actual flash spare area size. For example, for many NAND chip supporting ECC BCH-8, it has 226 bytes spare area. But controller can only uses 218 bytes. So brcmand driver overrides the mtd oobsize with the controller's accessible spare area size. When the nand base driver utilizes the nand_device object, it resets the oobsize back to the actual flash spare aprea size from nand_memory_organization structure and controller may not able to access all the oob area as mtd advises. This change fixes the issue by overriding the oobsize in the nand_memory_organization structure to the controller's accessible spare area size. Fixes: a7ab085d7c16 ("mtd: rawnand: Initialize the nand_device object") Signed-off-by: -
Backport of upstream Linux commit 5d53244186c9ac58cb88d76a0958ca55b83a15cd "mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write" When the oob buffer length is not in multiple of words, the oob write function does out-of-bounds read on the oob source buffer at the last iteration. Fix that by always checking length limit on the oob buffer read and fill with 0xff when reaching the end of the buffer to the oob registers. Signed-off-by:
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Backport from the Linux kernel: commit 9cc0a598b944816f2968baf2631757f22721b996 "mtd: rawnand: brcmnand: Fix potential false time out warning" If system is busy during the command status polling function, the driver may not get the chance to poll the status register till the end of time out and return the premature status. Do a final check after time out happens to ensure reading the correct status. Signed-off-by:
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Backport from the Linux kernel commit 2ec2839a9062db8a592525a3fdabd42dcd9a3a9b "mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller" v7.2 controller has different ECC level field size and shift in the acc control register than its predecessor and successor controller. It needs to be set specifically. Signed-off-by:
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Tom Rini authored
Merge tag 'u-boot-imx-next-20241005' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/22526 - Add DA9063 watchdog support for the imx6q-lxr2 board. - Add support for DH electronics i.MX8M Plus DHCOM PicoITX - Add DH i.MX8MP DHCOM SoM on DRC02 carrier board - Several fsl_esdhc_imx improvements. - Pas no-mmc-hs400 to mmc2 on imx8mm-cl-iot-gate.
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- Oct 04, 2024
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https://source.denx.de/u-boot/custodians/u-boot-snapdragonTom Rini authored
* Initial UFS PHY driver * Support for SM8150 (clock and pinctrl) * Allow writing configuration to PMIC GPIOs again * Support for configuring "special" pins (e.g. UFS reset or sdhc pins) * Support for "clk dump" command to decode various clocks.
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The series "rockchip: Add efuse and otp support to more SoCs" [1], merged in v2023.04, refactored and extended the Rockchip efuse and otp driver to support reading eFUSE/OTP for all supported Rockchip SoCs. Due to use of different licenses the drivers were never combined into a single driver, however anything non SoC specific should be applied to both drivers. The commit fe38b884 ("rockchip: Provided SPL control over efuse presence") changed Makefile options for only one of the two drivers, apply same change to keep these two drivers in sync. [1] https://lore.kernel.org/r/20230222224436.1570224-1-jonas@kwiboo.se/ Fixes: fe38b884 ("rockchip: Provided SPL control over efuse presence") Signed-off-by:
Jonas Karlman <jonas@kwiboo.se>
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Caleb Connolly authored
Drop in the RCG and GPLL data for debugging these clocks. Signed-off-by:Caleb Connolly <caleb.connolly@linaro.org>
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Caleb Connolly authored
Add "clk dump" support for SM6115. Signed-off-by: -
Caleb Connolly authored
Add debug data to dump PLL and RCG clocks. Signed-off-by: -
Caleb Connolly authored
Add support for dumping a few of the clocks used on Qualcomm platforms. Naming the Global PLL's, Root Clock Generators, and gate clocks. This helps a lot with platform bringup and feature enablement by making it easy to sanity check that the clocks are programmed correctly. == Usage == Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of qcom-<soc>.c. The "clk dump" command should print the states of all the gates, GPLLs and RCGs for your SoC. == Glossary == RCG: Root Clock Generator * Takes in some fairly arbitrary high freq clock (configurable clock source and options for taking just even pulses and other things) * Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary 8 or 16-bit values (depending on the RCG), and d is a number (with support for .5 offsets). GPLL: Global Phase Locked Loop * Crystal as input * integer multiplier + exponent part (2^-40) Gate: Simple on/off clock * Put between RCGs and the peripherals they power * Required to allow for correct power sequencing If you do the maths manually using the equations from "clk dump", the numbers should roughly line up by they're likely to be out by a handful of MHz. They output is formatted so that it can be pasted directly into the python interpreter. Signed-off-by: -
Caleb Connolly authored
This reverts commit 19f000b7. The bug in writing was caused by a long-standing error in the SPMI driver which has since been fixed - c2de620d ("spmi: msm: fix version 5 support"). We can safely enable writing GPIO configuration now. Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Add the special pins configuration data to allow setup the bias of the UFS and SDCard pins on the SM8250 SoC. Signed-off-by:
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Leverage the data introduced in the struct msm_special_pin_data to allow setting the gpio direction and value if supported by the pin data. Signed-off-by:
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Add Qualcomm QMP UFS PHY driver which is available on the following Snapdragon SoCs - SDM845, SM8250, SM8550 and SM8650 SoCs. Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by:
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Import Qualcomm QMP phy related header files from Linux v6.11-rc7, limit to headers needed to setup QMP v2 to v6 UFS PHYs. Signed-off-by:
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Enable clk and pinctrl for sm8150 Signed-off-by:
Julius Lehmann <lehmanju@devpi.de> Reviewed-by:
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Add pinctrl and GPIO driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This drivers differs from the similar U-Boot drivers, because SM8150 SoC have different function IDs for the same functions on different pins. Co-authored-by:
Volodymyr Babchuk <volodymyr_babchuk@epam.com> Reviewed-by:
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Add clock, reset and power domain driver for SM8150. Driver code is based on the similar U-Boot drivers. All constants are taken from the corresponding Linux driver. This driver supports clock rate setting only debug UART, RGMII/Ethernet modules and USB controller. Co-authored-by:
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Fabio Estevam authored
The LXR2 board has a DA9063 that can provide watchdog functionality. The DA9063 watchdog can cause a full POR reset, which is preferred over the built-in i.MX6 watchdog. Signed-off-by:Fabio Estevam <festevam@denx.de>
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Fabio Estevam authored
The DA9063 PMIC is a multi-function device that provides regulator, watchdog, RTC, and ON key functionalities. Add support for the DA9063 PMIC watchdog functionality. Based on the 6.11 kernel drivers/watchdog/da9063_wdt.c driver. Signed-off-by:
Stefan Roese <sr@denx.de>
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Marek Vasut authored
This shows up in 'help' output and introduces bogus gap: " mfgprot - Manufacturing Protection mii - MII utility commands " Drop the newline to fix this. Signed-off-by:
Marek Vasut <marex@denx.de> Acked-by:
Peng Fan <peng.fan@nxp.com>
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Ying-Chun Liu (PaulLiu) authored
The eMMC device on imx8mm-cl-iot-gate seems not support hs400. When booting 6.1.0 kernel we got the following error. mmc2: mmc_select_hs400es failed, error -110 mmc2: error -110 whilst initialising MMC card Add no-mmc-hs400 to mmc2 node solves the problem. Signed-off-by:Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
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Vitor Soares authored
With the introduction of downstream Linux 6.6, the iMX8MP VPU block control node in DTS was renamed "blk-ctl@38330000" and will not match the ones found in `node_path_imx8mp` resulting in the node not being disabled on the VPU-less variants. Add an extra node_path entry for imx8mp VPU block control that match with downstream Linux. Signed-off-by:
Vitor Soares <vitor.soares@toradex.com> Reviewed-by:
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Peng Fan authored
When supporting partition reset for SoC such as i.MX95 , the Linux Kernel may have configured the tuning, while after force reset by wdog or else, uboot CMD0 will never pass unless config RSTT to reset tuning logic. Since RSTA and RSTT are independent, so need both to be reseted in the controller. Acked-by:
Haibo Chen <haibo.chen@nxp.com> Signed-off-by:
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Ye Li authored
The memory of priv and plat are leaked if max_bus_width is wrong. Signed-off-by:
Ye Li <ye.li@nxp.com> Reviewed-by:
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Ye Li authored
The plat->cfg is wrongly memset to 0, so the host_caps value configured in fsl_esdhc_initialize is reset. Remove the unnecessary memset since plat is allocated via calloc. Reviewed-by:
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Ye Li authored
According to SD and MMC spec, 74 clocks must be sent to device after power stable. This is need in reinit ops for DM MMC or init ops for non-DM MMC after power cycle. So set the INTIA to send 80 clocks in esdhc_init_common and move its calling from probe to reinit. However, on 8MQ EVK and 8QXP MEK with some brands of SD cards, sending 80 clocks may not work well. The root cause is related with power up time. According to spec, after power stable, host shall supply at least 74 SD clocks to the SD card with the maximum of 1ms. However, the power ram up time is related with the characteristic of SD card. At the moment of sending 74 SD clocks, the power probably not ram up to the operating level on the problematic cards. Then cause the cards not ready. This patch changes to send SD clock with 1ms duration to replace 80 SD clocks (0.2ms at 400Khz clock). This way meets the spec requirement as well, and adds the margin for power ram up time to be compatible with the problematic SD cards. This is also aligned with implementation which has FORCE clock always on. Reviewed-and-tested-by:
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Peng Fan authored
With partition reset supported for i.MX8QM/QXP/95 and etc, when linux mmc runtime suspended, the mmc clks are gated off. While at same time system controller reset Cortex-A cores because of various reasons( WDOG timeout and etc), with SPL run again, only enable PER clk is not enough, also need to enable AHB/IPG clk, here use clk bulk API to enable all the clocks. Signed-off-by: -
Ye Li authored
So we can disable to build ADP5585 in SPL to save size Signed-off-by:
Alice Guo <alice.guo@nxp.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com>
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Marek Vasut authored
Add support for DH electronics i.MX8MP DHCOM SoM on DRC02 carrier board. This system is populated with two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Matching Linux kernel patch has been posted: https://lore.kernel.org/imx/20240925160343.84388-2-marex@denx.de/ Signed-off-by:
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Marek Vasut authored
Add support for DH electronics i.MX8M Plus DHCOM SoM on PicoITX carrier board. This system is populated with serial console, EQoS ethernet, eMMC, SD, SPI NOR, LEDs and USB 3.0 host used in USB 2.0 mode on PicoITX. Matching Linux kernel patch has been posted: https://lore.kernel.org/imx/20240928234949.357893-2-marex@denx.de/ Signed-off-by:
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- Oct 03, 2024
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Tom Rini authored
Merge tag 'u-boot-dfu-next-20241003' of https://source.denx.de/u-boot/custodians/u-boot-dfu into next u-boot-dfu-next-20241003 CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/22516 DFU: - Reinitialize only if dfu_alt_info changed USB Gadget: - New usb gadget driver for Renesas USBHS - Simplify kconfig deps for CMD_USB_MASS_STORAGE Android: - Provide bootloader version to android via kernel commandline
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Tom Rini authored
Simon Glass <sjg@chromium.org> says: This includes various patches towards implementing the VBE abrec bootmeth in U-Boot.
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This driver should not generally be present in SPL, even if misc devices are enabled. Update the Makefile rule accordingly. Signed-off-by:Simon Glass <sjg@chromium.org>
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Add a missing colon and newline in rk3399_emmc_get_phy(). Signed-off-by:
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