- Apr 01, 2016
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To simplify support for new SoCs, just use a constant filename for the unknown case. In practice this case shouldn't be hit anyway, so the filename isn't relevant, and certainly doesn't need to differentiate between SoCs. If a user has an as-yet-unknown board, they can override this value in the environment anyway. Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Signed-off-by:
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Add some basic clarification that the dev.key file generated by OpenSSL contains both the public and private key, and further highlight that the certificate generated here contains the public key only. Signed-off-by:Andreas Dannenberg <dannenberg@ti.com>
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Different sections in the document suggest flattened image tree blob files have a file name extension of .itb. Fix the list of file extensions to reflect that. Signed-off-by: -
It is clearer to specify the full path to access the doc/README.displaying-bmps file. Signed-off-by:Fabio Estevam <fabio.estevam@nxp.com>
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Add missing Privilege ID settings for KS2 SoCs. Based on: K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013) http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99) K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015) http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71) K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015) http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75) K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016) http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238) Overall mapping: -------+-----------+-----------+-----------+--------- PrivID | KS2H/K | K2L | K2E | K2G -------+-----------+-----------+-----------+--------- 0 | C66x 0 | C66x 0 | C66x 0 | C66x 0 1 | C66x 1 | C66x 1 | Reserved | ARM 2 | C66x 2 | C66x 2 | Reserved | ICSS0 3 | C66x 3 | C66x 3 | Reserved | ICSS1 4 | C66x 4 | Reserved | Reserved | NETCP 5 | C66x 5 | Reserved | Reserved | CPIE 6 | C66x 6 | Reserved | Reserved | USB 7 | C66x 7 | Reserved | Reserved | Reserved 8 | ARM | ARM | ARM | MLB 9 | NetCP | NetCP | NetCP | PMMC 10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS 11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC 12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP 13 | Reserved | Reserved | PCIe_1 | Reserved 14 | HyperLink | PCIe_1 | HyperLink | Reserved 15 | Reserved | Reserved | TSIP | Reserved -------+-----------+-----------+-----------+--------- NOTE: Few of these might have default configurations, however, since most are software configurable, it is better to explicitly configure the system to have a known default state. Without programming these, we end up seeing lack of coherency on certain peripherals resulting in inexplicable failures (such as USB peripheral's DMA data not appearing on ARM etc and weird workarounds being done by drivers including cache flushes which tend to have system wide performance impact). By marking these segments as shared, we also ensure SoC wide coherency is enabled. Reported-by:
Bin Liu <b-liu@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: -
MSMC segment Privilege ID is not consistent accross the keystone2 SoCs. As the first step to ensure complete SoC wide coherency setup, lets refactor the macros to remove the #if-deffery around the code which obfuscates which IDs are actually enabled for which SoC. As a result of this change the PCIe configuration is moved after the msmc configuration is complete, but that should ideally have no functional impact. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
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smsc95xx_read_reg() should calculate sizeof(*data) not sizeof(data) since data is a pointer, and the value pointed at is being transferred over USB, not the value of the pointer. This fixes operation of the driver in 64-bit builds, such as the Raspberry Pi 3. Reported-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
Marek Vasut <marex@denx.de> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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Command parsing and processing code is not needed when the command line is disabled. Remove this code in that case. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
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Some boards need to expose device specific variable through fastboot (to adpat the flashing script depending on hardware revision for example). Provide a way to expose custom fastboot variables. Note that all variables meant to be exposed through fastboot should be be prefixed with 'fastboot.', the variable should not exceed 32 bytes (including the prefix and the trailing '\0') and the variable content should fit in the response buffer (60 bytes excluding the 'OKAY' prefix and the trailing '\0'). Signed-off-by:
Rob Herring <rob.herring@linaro.org> [Boris Brezillon: add a commit message] Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
Steve Rae <srae@broadcom.com>
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Tom Rini authored
- Move most of the flags required into LLVM_RELFLAGS to test at build time instead of requiring them to be passed in. - Update doc/README.clang to reflect this - Switch to rpi_2 as the example as it's closer to working out of the box than rpi is. Cc: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: -
http://git.denx.de/u-boot-sunxiTom Rini authored
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Alexander Graf authored
On the A64 we usually boot with ATF running in EL3. ATF as it is available today resides in the first 16MB of RAM. So we should make sure we reserve that space in our memory maps. Signed-off-by:
Alexander Graf <agraf@suse.de> Acked-by:
Hans de Goede <hdegoede@redhat.com> Signed-off-by:
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Siarhei Siamashka authored
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of running AArch64 code and thus is the first of its kind for the sunxi target. This patch adds a defconfig and device tree chunks for it. Signed-off-by:
Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: Change patch description] Signed-off-by:
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Siarhei Siamashka authored
The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by:
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Alexander Graf authored
Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by:
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Alexander Graf authored
We currently depend SPL config options on specific machine types which doesn't scale. Fortunately there's already a kconfig variable that tells us whether we want to build SPL code at all, so just depend them on this. Signed-off-by:
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Alexander Graf authored
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by:
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Chen-Yu Tsai authored
This provides the minimal changes to the H8Homlet v2 dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Reviewed-by:
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Chen-Yu Tsai authored
This provides the minimal changes to the Cubietruck Plus dts to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by:
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Chen-Yu Tsai authored
This provides the minimal changes to the A83T dtsi to enable USB in U-boot. It is not what will be submitted to the kernel. Signed-off-by:
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Chen-Yu Tsai authored
The Cubietruck Plus uses all 3 USB controllers: - USB OTG functions are provided by the musb USB OTG controller - Onboard SATA is provied by a USB-SATA bridge connected to USB1 - The USB host ports on the board are provided by an HSIC USB hub FLDO1 is set to 1.2V for HSIC. Signed-off-by:
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Chen-Yu Tsai authored
The h8_homlet_v2 has 2 USB host ports, one connected to the OTG controller, one connected to the EHCI/OHCI pair. Also provide the card detect pin for MMC. Signed-off-by:
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- Mar 31, 2016
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Masahiro Yamada authored
I no longer see the problem claimed in the comment block. Rather, the 0.5 msec timeout seems too short for some TFTP servers. Drop the CONFIG_ARM_TIMEOUT to fall back to the 5 sec timeout. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Signed-off-by: -
Masahiro Yamada authored
Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: -
Masahiro Yamada authored
Signed-off-by: -
Masahiro Yamada authored
On PH1-sLD3, eMMC and NAND are assigned to different I/O pins. Both devices can be enabled at the same time. Signed-off-by: -
Masahiro Yamada authored
Currently, these functions assume #address-cells and #size-cells are both one. Fix them to support 64bit DTB. Also, I am fixing a buffer overrun bug while I am here. The array size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of iteration in the loop should be limited by that CONFIG. Signed-off-by: -
Masahiro Yamada authored
These defined were used for pre-DM ns16550 serial driver. They are unneeded because UniPhier SoCs now use DM serial. Signed-off-by: -
Masahiro Yamada authored
This will be used to set up pin-muxing for the NAND controller. Signed-off-by: -
Masahiro Yamada authored
Since no clock driver is implemented for peripherals in U-Boot yet, this property is needed for the serial driver to set up the divisor register. Signed-off-by: -
Masahiro Yamada authored
The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20 (as far as used in boot-loader), so this commit makes the driver shared between the two SoCs. Signed-off-by: -
Masahiro Yamada authored
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: -
Masahiro Yamada authored
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit prepares the core part for that. Signed-off-by: -
Masahiro Yamada authored
The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: -
Masahiro Yamada authored
Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: -
Masahiro Yamada authored
Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: -
Masahiro Yamada authored
Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: -
Masahiro Yamada authored
Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by:
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