- Mar 30, 2021
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Robert Hancock authored
The code was trying to disable PCS auto-negotiation when a fixed-link node is present and enable it otherwise. However, the PCS registers were being written before the PCSSEL bit was set in the network configuration register, and it appears that in this state, PCS register writes are ignored. The result is that the intended change only took effect on the second network operation that was performed, since at that time PCSSEL is already enabled. Fix the order of register writes so that PCS registers are only written to after the PCS is enabled. Fixes: 26e62cc9 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by:
Robert Hancock <robert.hancock@calian.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com> Reviewed-by:
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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- Mar 23, 2021
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Linux commit a75bbe71a27 ("mtd: rawnand: fsl_ifc: fix FSL NAND driver to read all ONFI parameter pages") Per ONFI specification (Rev. 4.0), if the CRC of the first parameter page read is not valid, the host should read redundant parameter page copies. Fix FSL NAND driver to read the two redundant copies which are mandatory in the specification. Signed-off-by:Jane Wan <Jane.Wan@nokia.com> Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by:
Maxim Kochetkov <fido_max@inbox.ru> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code allocate memory for the struct ls_pcie with random contents, this can result in skipping to assign the ls_pcie->ctrl with the 'lut' address, then further crash with the incorrect address. Fixes: 118e58e2 ("pci: layerscape: Split the EP and RC driver") Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by:
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As far as u-boot is concerned the ds1339 is compatible with the other devices supported by the ds1307 driver. The Linux driver does expose some additional functionality but as far as u-boot is concerned just adding the compatible string is enough. Signed-off-by:
Chris Packham <judge.packham@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
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- Mar 19, 2021
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At the moment the nvme_get_features() and nvme_set_features() functions carry a (somewhat misleading) comment about missing cache maintenance. As it turns out, nvme_get_features() has no caller at all in the tree, and nvme_set_features' only user doesn't use a DMA buffer. Mention that in the comment, and leave some breadcrumbs for the future, should those functions attract more users. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
At the moment nvme_read_completion_status() tries to invalidate a single member of the cqes[] array, which is shady as just a single entry is not cache line aligned. The structure is dictated by hardware, and with 16 bytes is smaller than any cache line we usually deal with. Also multiple entries need to be consecutive in memory, so we can't pad them to cover a whole cache line. As a consequence we can only always invalidate all of them - U-Boot just uses two of them anyway. This is fine, as they are only ever read by the CPU (apart from the initial zeroing), so they can't become dirty. Make this obvious by always invalidating the whole array, regardless of the entry number we are about to read. Also blow up the allocation size to cover whole cache lines, to avoid other heap allocations to sneak in. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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The module defines a duplicate uclass driver for UCLASS_SIMPLE_BUS, but it is not allowed. This breaks of-platdata and makes the result non-deterministic. The driver does not need to be an uclass driver, so lets remove it. I had turned it into an uclass driver because I thought wrongly it had to call the dm_scan_fdt_dev routine to work properly, but some tests on the board have shown otherwise. Signed-off-by:
Dario Binacchi <dariobin@libero.it> Reviewed-by:
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building with MTK_AHCI enabled results in implicit declaration and undefined reference of dev_err followed by a segfault of gcc drivers/ata/mtk_ahci.c: In function 'mtk_ahci_parse_property': drivers/ata/mtk_ahci.c:65:4: warning: implicit declaration of function 'dev_err' drivers/ata/mtk_ahci.c:65: undefined reference to `dev_err' in function `mtk_ahci_probe': drivers/ata/mtk_ahci.c:92: undefined reference to `dev_err' Segmentation fault fix this by adding the dm/device_compat.h to includes Signed-off-by:Frank Wunderlich <frank-w@public-files.de>
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- Mar 17, 2021
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commit e58e68d9 ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value") wrongly assumed that plat->cfg.f_max is always unset at the time mscd_drv_probe() is run. This is not true in case max-frequency being defined in device tree, as it is then already set by mmc_of_parse() in msdc_of_to_plat(). Only set plat->cfg.f_max to the default maximum value in case it is not already set to a sane value. Fixes: e58e68d9 ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value") Cc: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by:
Daniel Golle <daniel@makrotopia.org>
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- Mar 12, 2021
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Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: -
The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have different bounds declared in header files where these variables are also defined from the ones declared in source files. This causes the compiler to complain (when building with LTO): ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match original declaration [-Wlto-type-mismatch] ddr3_patterns_64bit.h:911:5: note: array types have different bounds ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously declared here ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:167:4: note: array types have different bounds ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared here ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:196:4: note: array types have different bounds ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared here CI managed to trigger this as an error when compiling with LTO for AXP. Fix this by using values from the header files, which seem to be the correct ones. Signed-off-by:Marek Behún <marek.behun@nic.cz>
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In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common XOR definitions, regardless whether we compile for axp or a38x. But the declaration of this function has a different signature in axp's xor.h from the one used in a38x' implementation - one parameter is u64 instead of u32. This can result in wrong argument's being passed to that function on a38x with no one the wiser. I discovered this when building U-Boot for Turris Omnia with LTO. The compiler complains about the different signatures being thrown into the same linking process: axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match original declaration [-Wlto-type-mismatch] 67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, | ^ a38x/xor.c:165:5: note: type mismatch in parameter 3 165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long | ^ a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match type ‘u32’ Fix this by changing the type of the block_size argument in the axp's implementation and header file to the one used in a38x (and upstream mv-ddr-marvell). Signed-off-by: -
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot"). This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x and ddr3: files=drivers/ddr/marvell/a38x/* sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files 3. Manually omit SPDX-License-Identifier changes from this patch as upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x ddr3 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch is removal of dead code and some fixes with include files. Signed-off-by:
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commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream. At this moment, only page 0 of SPD is being read but to support smbios, we need to read page 1 also which has more info. In order to do that, we need to allocate more space. Signed-off-by:
Sujeet Baranwal <sujeet.baranwal@cavium.com> Tested-by:
sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by:
Nadav Haklai <nadavh@marvell.com> Signed-off-by:
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- Mar 11, 2021
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The DSI phy can be turned on from the DSI digital interface in the dphy_enable() function or from a dedicated DSI phy "wrapper" in phy_ops->init() function. If the STM32MP1 case, the wrapper is used then the dphy_enable() "warning" traces are not relevant. This patch moves these "warning" traces to "debug" traces so they are still available for DSI phy based on the digital interface in debug logging mode, but not there in normal mode for both cases. Note: The related Linux kernel driver uses a "debug" message too. Signed-off-by:
Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Missing udevice to struct dw_mipi_dsi to log trace. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: -
Remove the child device of the STM32 DSI bridge when the driver probe failed to stop futher probe request on panels used with STMicroelectronics board (orisetech_otm8009a.c or raydium-rm68200.c driver). This patch avoid the trace "cannot get reset GPIO" when STM32MP157 device tree is used on stm32MP151 SOC without DSI support. In this hw_version value is 0, as DSI bridge is absent and the panel ofdata_to_platdata is called for each try of panel probe, the gpio reset pin is requested but after dsi father probe failed). For the next request, the PANEL ofdata_to_platdata failed as the gpio is already used. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: -
Reorder include files in expected order. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: -
Define LOG_CATEGORY to allow filtering with log command. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: -
Include the file needed for log function prototype, this patch solves the compilation issue for undefined reference to `dev_err'. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: -
This change makes stm32mp1 clock driver to get the root clocks reference from the device node in the FDT rather than fetching straight these clocks by their name. Driver now stores the clock reference and use it to know if a root clock is present, get its rate or gets its related udevice reference. Signed-off-by:
Etienne Carriere <etienne.carriere@st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: -
Patrice Chotard authored
In case of big area read/write on spi nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and spinand_mtd_write() to ensure that watchdog is reset. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> -
Patrice Chotard authored
In case of big area erased on nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that watchdog is reset. Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> -
Patrice Chotard authored
In case of reading large area and memory-map mode is misconfigured (memory-map size declared lower than the real size of the memory chip) watchdog can be triggered. Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it. Issue reproduced with stm32mp157c-ev1 board and memory map size set to 1, with following command: sf read 0xC0000000 0 0x4000000 Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com> -
Patrice Chotard authored
In case of big area write/erase on spi nor, watchdog timeout may occurs. Issue reproduced on stm32mp157c-ev1 with following commands: sf write 0xC0000000 0 0x3000000 or sf erase 0 0x1000000 Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
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- Mar 10, 2021
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When flush cache of the current GPD and resume QMU, the controller will try to access the next GPD after processing the current one, if not flush the next GPD, the controller may get wrong GPD status. Signed-off-by:Chunfeng Yun <chunfeng.yun@mediatek.com>
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- Mar 09, 2021
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This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed a typo in arch/x86/Kconfig]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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- Mar 08, 2021
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Neil Armstrong authored
Fix the treshold typo in code by threshold. Fixes: c0165c85 ("button: add a simple Analog to Digital Converter device based button driver") Suggested-by:
Tom Rini <trini@konsulko.com> Signed-off-by:
Marek Szyprowski <m.szyprowski@samsung.com>
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Siew Chin Lim authored
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by:Siew Chin Lim <elly.siew.chin.lim@intel.com>
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- Mar 05, 2021
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sysreset uclass driver provides an implementation of 'reset' command using the sysreset_ APIs unconditionally. It also supports the 'poweroff' command using the sysreset_ APIs, but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF. Let's do the same for the 'reset' command, by introducing a new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to on by default, to allow a board that don't have a sysreset reset driver yet, but have a sysreset poweroff driver to compile without any issue. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
The VirtIO BLK driver depends on the blk uclass driver. Add the dependency in the Kconfig. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by:
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devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Commit e0024741 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e0024741 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by:
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- Mar 04, 2021
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A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Currently ns16550_serial_assign_base() treats the argument 'base' with type `ulong`. This is incorrect because the base address was obtained from device tree with type `fdt_addr_t` that can represent a physical address larger than 32-bit in a 32-bit system. Fixes: 9e6ce621 ("serial: ns16550: Fix ordering of getting base address") Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Each invocation of the 'host bind' command with a file name argument opens a file descriptor. The next invocation of the 'host bind' command destroys the block device but the file descriptor remains open. The same holds true for the 'unbind blk' command. Close the file descriptor when unbinding the host block device. Signed-off-by:
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