- Feb 26, 2021
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The code was processed with unifdef utility to omit portions not relevant to A38x and DDR3. This removes usage of many macros, including A70X0, A80X0 and A3900. It seems that the unifdef utility did not remove the macros from #else comment. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Tested-by:
Chris Packham <chris.packham@alliedtelesis.co.nz>
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Bump version of a38x DDR3 trianing to version 14.0.0 to reflect the version in the mv-ddr-devel branch of upstream repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git . There is a new version numbering system, where after 18.12.0 came 1.0.0, 2.0.0, and so on until 14.0.0. So 14.0.0 is newer than 18.12.0. Signed-off-by:
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commit 56db5d1464b44df10a02b99e615ebd6f6a35c428 upstream. @pali suggested this change In commit 6285efb ("mv_ddr: add support for twin-die combined memory device") was added support for twin-die combined memory device and default value for explicitly uninitialized structure members is zero, s also twin_die_combined is initialized to zero. Which means COMBINED value. As prior this commit there was no support for twin-die combined memory device, default value for twin_die_combined should be NOT_COMBINED. This change change order of enum mv_ddr_twin_die to ensure that NOT_COMBINED has value zero. Signed-off-by:heaterC <airyguy@gmx.de> Signed-off-by:
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commit 2bdd12dd68b1f8e27a03a3443ae49a09a14c18e4 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes code in ddr3_training.c. Import this change to remain consistent with upstream. Signed-off-by:
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commit c8b301463d508c807a33f7b7eaea98bbda4aa35e upstream. The funtion returnd cs size in byte instead of MB, that cause calculation error since the caller was expected to get u32 and when he got above 4G it refers it as 0. The fix was to get the cs memory size from function as in MB and then multiply it by 1MB. Signed-off-by:
Moti Buskila <motib@marvell.com> Reviewed-by:
Kostya Porotchkin <kostap@marvell.com> Signed-off-by:
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commit d653b305d0b3da9727c49124683f1a6d95d5c9a5 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by:
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commit 20c89a28548cdab11f88d2ec8936344af0686a1e upstream. WL phase correcion stage is failing while using bus_width of 16bit, not to be fix this stage is un-necessary when working with bus_width of 16 bit. Signed-off-by:
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commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream. the twin-die combined memory device should be treatened as X8 device and not as X16 one Signed-off-by:
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commit 994509eb4fe6771d92cd06314c37895098ac48fa upstream. Signed-off-by:
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commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream. The ODT enable heuristic based on active chip-selects is not always correct. Some board might use two chip-selects, but have only one ODT line connected. Allow board specific mv_ddr_topology_map to directly set the ODT configuration register value. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Reviewed-by:
Nadav Haklai <Nadav.Haklai@cavium.com> Reviewed-by:
Kostya Porotchkin <Kostya.Porotchkin@cavium.com> Signed-off-by:
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commit 3908e20c6c520339e9bddb566823ae5e065d5218 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by:
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commit ab9240402a70cc02496683971779e75eff410ab4 upstream. - function mv_ddr_spd_die_capacity_user_get() has a bug, since it insert a user memory enum to it, instead of SPD memory enum (which are different) - fix: remove mv_ddr_spd_die_capacity_user_get() function. - memory size with 64 and 32 bit already calculated correctly at mv_ddr_mem_sz_per_cs_get() function Signed-off-by:
Stefan Chulski <Stefan.Chulski@cavium.com> Reviewed-by:
Alex Leibovich <alexl@marvell.com> Reviewed-by:
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commit 0b5adedd4ced9b8f528faad1957d4d69e95759ef upstream. Signed-off-by:
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commit 6c705ebc0d70f67ed7cae83ad1978c3305ef25be upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header mv_ddr_topology.h. Import this header change to remain consistent with upstream. Signed-off-by:
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commit 61a8910998d7b553e80f600ebe8147a8b98f0945 upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by:
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commit 32800667b375ebd1f82120da0f3479b1cf52d96d upstream. Required changes made for 32bit ddr support. An update is made to the topology map, according to bus_act_mask, set in the dram_port.c Signed-off-by:
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commit a165037ec26f301be75e1fabc263643683e85255 upstream. The commit mentioned above changes non-DDR3 stuff in upstream, but it also changes header ddr_topology_def.h. Import this header change to remain consistent with upstream. Signed-off-by:
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commit ce62bef8fac559e27245259882e45f19cdc293ad upstream. - fix JIRA A7K8K-5056 - remove TEST_PATTERN write at the load patern stage earlier to WL SUP stage - the WL SUP stage already writes this pattern to the memory, if the pattern exist at the memory then the algorithm will fail, since it think that there are no phase to correct Signed-off-by:
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The SPI NOR flash node name in main device tree for Turris Omnia is called `spi-nor@0`. Rename node spi-flash@0 in Turris Omnia's -u-boot.dtsi file to spi-nor@0 so that U-Boot does not try to probe the same SPI NOR device multiple times. Signed-off-by:
Stefan Roese <sr@denx.de> Reviewed-by:
Pali Rohár <pali@kernel.org>
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Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by:
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Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by:
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Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by:
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Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by:
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PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by:
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NVMe drives can be connected to Turris MOX via MOX B and MOX G extensions. Signed-off-by:
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USB devices can be connected to Turris MOX also via MOX F extension which contains VL805 PCIe based USB 3.0 controller. Signed-off-by:
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PCIe devices do not work in U-Boot without proper initialization and configuration of PCI config space like the PCI_BASE_ADDRESS_0 register. Signed-off-by:
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Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by:
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- Feb 25, 2021
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Tom Rini authored
- Remove various older platforms that are missing DM migrations and have had their removal ack'd.
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Tom Rini authored
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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Tom Rini authored
In the cases of T2080RDB_SECURE_BOOT, T2080RDB_SRIO_PCIE_BOOT, P2041RDB_SECURE_BOOT, P2041RDB_SRIO_PCIE_BOOT, P3041DS_SRIO_PCIE_BOOT and P4080DS_SRIO_PCIE_BOOT while some forms of the board have been migrated more fully to current build standards, these have not. Remove them. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by:
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Tom Rini authored
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Stefano Babic <sbabic@denx.de> Signed-off-by:
Stefano Babic <sbabic@denx.de>
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Tom Rini authored
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com>
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Tom Rini authored
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Tom Rini authored
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Tom Rini authored
- squashfs, btrfs fixes - Kconfig CONFIG logic fixes - hikey DM migration - Some portability fixes for the build system - Assorted code cleanups
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- Feb 24, 2021
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Commit "common: Drop asm/global_data.h from common header" added asm/global_data.h into secure.h. However, secure.h will be included by psci.S. Adding asm/global_data.h has caused compilation failure in pcsi.S. Add "ifndef __ASSEMBLY__" in asm/global_data.h. Signed-off-by:
Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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When copying to a u32 field we should use sizeof(u32) and not sizeof(*u32) in memcpy. On 64bit systems like cortina_presidio-asic-emmc_defconfig using sizeof(*u32) leads to a buffer overrun. Fixes: febe13b4 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs") Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-By:
Ramon Fried <rfried.dev@gmail.com>
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ca_do_bch_correction() takes a random value from the stack and starts counting bitflips from this value. Initialize the counter. This passed unnoticed as the value is finally ignored in the call hierarchy. Fixes: 161df94b ("mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support") Signed-off-by:
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The values of left_edge[0] and right_edge[0] are overwritten before they are used. Remove the superfluous assignments. Fixes: 285b3cb9 ("dm: ddr: socfpga: fix gen5 ddr driver to not use bss") Signed-off-by:
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