- Feb 08, 2022
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The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by:Aswath Govindraju <a-govindraju@ti.com>
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Add support for ipu early boot. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Amjad Ouled-Ameur <aouledameur@baylibre.com>
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Add support for ipu early boot. Signed-off-by:
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Add ipu and the associated nodes. Signed-off-by:
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Add all the ipu early boot related nodes Signed-off-by:
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Enable fs_loader compilation at SPL Level. Signed-off-by:
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First check the presence of the ipu firmware in the boot partition. If present enable the ipu and the related clocks & then move on to load the firmware and eventually start remoteproc IPU1/IPU2. do_enable_clocks by default puts the clock domains into auto which does not work well with reset. Hence adding do_enable_ipu_clocks function. Signed-off-by:
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J721S2 can support two instances for DDR. Therefore, add the device support for the same and use 4266MT/s as DDR frequency. Signed-off-by: -
Add initial support for device tree that runs on R5. Signed-off-by: -
The EVM architecture for J721S2 is similar to that of J721E and J7200. It is as follows, +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the common processor baord. Therefore, add support for peripherals brought out in the common processor board. Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439 Signed-off-by: -
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Therefore, add support for the components present on the SoM. Signed-off-by: -
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 Introduce basic support for the J721S2 SoC. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com>
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Add basic support for J721S2 SoC definition Signed-off-by:
David Huang <d-huang@ti.com> Signed-off-by:
Dave Gerlach <d-gerlach@ti.com> Signed-off-by:
Hari Nagalla <hnagalla@ti.com>
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- Feb 07, 2022
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This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB IT V1.0B module. They are strapped to boot from eFuses which are factory fused to properly boot from their on-module eMMC. U-Boot supports booting from the on-module eMMC only, SDP support is disabled for now due to missing i.MX 8M Plus USB support. Functionality wise the following is known to be working: - eMMC, 8-bit and 4-bit MMC/SD card slots - Ethernet both on-module eQoS and FEC (requires PHY on carrier board) - GPIOs - I2C Boot sequence is: SPL ---> ATF (TF-A) ---> U-boot proper ATF, U-boot proper and u-boot.dtb images are packed into a FIT image, loaded by SPL. Boot: U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100) Quad die, dual rank failed, attempting dual die, single rank configuration. Normal Boot WDT: Started watchdog@30280000 with servicing (60s timeout) Trying to boot from BOOTROM Find img info 0x&48025a00, size 872 Need continue download 1024 Download 779264, Total size 780424 NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b NOTICE: BL31: Built : 16:52:37, Aug 26 2021 U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100) CPU: Freescale i.MX8MP[8] rev1.1 at 1200 MHz Reset cause: POR DRAM: 8 GiB Core: 78 devices, 18 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281 Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609 Setting variant to wifi Net: Hard-coding pdata->enetaddr eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME] Hit any key to stop autoboot: 0 Verdin iMX8MP # Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com>
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- Feb 05, 2022
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The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor. Signed-off-by:Heiko Thiery <heiko.thiery@gmail.com>
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SION (Software Input On Field) - force the select mode input path Signed-off-by:Angus Ainslie <angus@akkea.ca>
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Update to the 5.16 imx8mq dts files and dt bindings Changes since v1: Dropped rfkill.h that is not in linux mainline yet. Signed-off-by:
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Commit 97c16dc8 ("imx: mx6ull: update the REFTOP_VBGADJ setting") made this macro unused. Then remove it. Signed-off-by:
Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by:
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The previous code wrote the contents of the fuse as is in the REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of the table in the code comment. This table is also different from the table in the commit description. But then, which of the two is correct? If it is assumed that an unprogrammed fuse has a value of 0 then for backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to 6 (b'110). Therefore, the table in the code comment can be considered correct as well as this patch. Fixes: 97c16dc8 ("imx: mx6ull: update the REFTOP_VBGADJ setting") Signed-off-by:
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Add the PCIe support on i.MX8MM platforms. Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Tested-by:
Tim Harvey <tharvey@gateworks.com> Tested-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support")
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Add the PCIe PHY support on iMX8MM platforms. Signed-off-by:
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Add board dts for Advantech's imx8mp-rsb3720-a1 Signed-off-by:
Darren Huang <darren.huang@advantech.com.tw> Signed-off-by:
Kevin12.Chen <Kevin12.Chen@advantech.com.tw> Signed-off-by:
Phill.Liu <Phill.Liu@advantech.com.tw> Signed-off-by:
Tim Liang <tim.liang@advantech.com.tw> Signed-off-by:
wei.zeng <wei.zeng@advantech.com.cn> Signed-off-by:
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: uboot-imx <uboot-imx@nxp.com>
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The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020 documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the pinmux tables. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by:
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Fix address of the pad control register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems to be a typo but it leads to an exception when pinctrl is applied due to wrong memory address access. Signed-off-by:
Oliver Stäbler <oliver.staebler@bytesatwork.ch> Reviewed-by:
Rob Herring <robh@kernel.org> Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm") Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ") Signed-off-by:
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Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs in case they should be operated faster, e.g. to improve boot time. Signed-off-by: -
Linux uses slightly different divider settings for the 1.2 GHz PLL configuration, adjust the coefficients to match Linux. Signed-off-by: -
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfb ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c7181 ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by:
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>
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With the updated device tree's having USB support, enable in U-Boot. This also requires the addition of the imx8m power domain, since the USB is gated by the power domain controller. Signed-off-by:
Adam Ford <aford173@gmail.com> Reviewed-by:
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Resync the SOM and baseboar files with the device trees that will be included in 5.17-RC1 when it's cut. This will improve pinmuxing for USDHC1 and add USB functionality. Signed-off-by:
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As suggested in commit 028abfd9 ("imx8mm-evk: Generate a single bootable flash.bin again") for imx8mm_evk, it is possible to produce single bootable image via binman. This restores the original behavior in distros, where only one boot container is used to create target image. Perform similar adaptions in order to provide single bootable image for imx8mn-ddr4-evk derivate. Update documentation to drop additional step of copying u-boot.itb Fixes: 353dfe4b ("imx8mn-ddr4-evk: switch to use binman") Signed-off-by:
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Rather than using odd implicit blob-ext naming, explicitly specify the type to be of blob-ext and therefore also simplify the node naming. Signed-off-by:
Patrick Wildt <patrick@blueri.se> Reviewed-by:
Fabio Estevam <festevam@denx.de>
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Some of the nodes were named using a underscore, so rectify this and consistenly use dashes. Signed-off-by:
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Explicitly add SPL aka u-boot-spl.bin filename. Signed-off-by:
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Alphabetically re-order properties. Signed-off-by:
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When using a board variant that selects the lvds specific dtb the *.u-boot.dtsi file will not be included. To have a lvds dtb specific u-boot.dtsi file move this part to a common board u-boot.dtsi file and include this in the board base u-boot.dtsi and create an additional one for the lvds variant. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de>
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Add support of secondary boot address for imx8mn. The secondary boot address is hardcoded in the fuse. The value is calculated from there according to the following description: The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows: - Secondary boot is disabled if fuse value is bigger than 10, n = fuse value bigger than 10. - n == 0: Offset = 4MB - n == 2: Offset = 1MB - Others & n <= 10 : Offset = 1MB*2^n - For FlexSPI boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7. Signed-off-by:Michael Trimarchi <michael@amarulasolutions.com>
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Similar to what has been done before with c5437e5b for u-boot proper, we enable the SMP bit for SPL as well. This is necessary when SDP booting straight into Linux, i.e. falcon boot. When SDP boot mode is active, the ROM code does not set this bit which makes the caches not work once activated in Linux. On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into an initramfs shell from ~6.1s down to ~1.2s. Signed-off-by:
Sven Schwermer <sven@svenschwermer.de> Reviewed-by:
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Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12"). There is no functional change to the resulting DTs. The imx6qdl-dhcom-pdk2.dtsi had to be adjusted with additional headers, gpio.h, pwm.h, input.h, else the DT cannot be compiled, the same change is likely necessary in Linux. Signed-off-by: -
Add labels to remaining anatop regulators, so their supplies can be assigned in board DTs. This is similar to Linux kernel commit 93385546ba369 ("ARM: dts: imx6qdl-sabresd: Assign corresponding power supply for LDOs") except it does not contain the unrelated sabresd changes. Signed-off-by: -
This change enables the support for USB with DM on the XEA (imx28) board. Signed-off-by:Lukasz Majewski <lukma@denx.de>
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