Skip to content
Snippets Groups Projects
  1. May 15, 2020
  2. May 14, 2020
    • Jan Kiszka's avatar
      kbuild: spl: Add shrunk arch-dtbs to targets list · 5f09f9af
      Jan Kiszka authored and Tom Rini's avatar Tom Rini committed
      
      This avoids needless rebuilding.
      
      Fixes: 2f57c951 ("spl: dm: Make it possible for the SPL to pick its own DTB from a FIT")
      CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      5f09f9af
    • Jan Kiszka's avatar
      kbuild: spl: Fix parallel build · 5d3534de
      Jan Kiszka authored and Tom Rini's avatar Tom Rini committed
      
      The dts dir must exists when running this rule.
      
      That missing dependency broke e.g. "make -j" for the am65x targets.
      
      Fixes: 2f57c951 ("spl: dm: Make it possible for the SPL to pick its own DTB from a FIT")
      CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
      Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
      5d3534de
    • Tom Rini's avatar
      Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm · e2b86e23
      Tom Rini authored
      - stm32mp1: migrate MTD and DFU configuration in Kconfig
      - stm32mp1: add command stm32prog
      - stm32mp1: several board and arch updates
      - stm32mp1: activate data cache in SPL and before relocation
      - Many improvment for AV96 board and DHCOR SoM
        (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
         Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
      - clk: stm32mp1: fix CK_MPU calculation
      - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
      e2b86e23
    • Tom Rini's avatar
      Merge tag 'rpi-next-2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi · fe167861
      Tom Rini authored
      - fix phy configuration for RPi4's bcmgenet
      - sync RPi4's env size with other RPi configs
      - add kconfig option to reserver more pages in the EFI mem map
      - add support for SDMA which is used by RPi4
      - fix corner case boot bug for RPi3 32-bit
      fe167861
    • Patrick Delaunay's avatar
      ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2 · 1b28a5e2
      Patrick Delaunay authored
      
      DT alignment with Linux 5.7-rc2, including the kernel commits
      
      431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards
      79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards
      877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards
      7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards
      f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1
      d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x
      b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c
      1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1
      bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1
      b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx
      a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards
      8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1
      fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board
      cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151
      c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1
      9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15
      82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151
      8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node
      a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1
      4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1
      80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1
      ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1
      
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      1b28a5e2
    • Lionel Debieve's avatar
      clk: stm32mp1: fix CK_MPU calculation · 36911fca
      Lionel Debieve authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      When the CK_MPU used PLL1_MPUDIV, the current rate is
      wrong. The clock must use stm32mp1_mpu_div as a shift
      value. Fix the check value used to enter PLL_MPUDIV.
      
      Signed-off-by: default avatarLionel Debieve <lionel.debieve@st.com>
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      36911fca
    • Patrick Delaunay's avatar
      mmc: stm32_sdmmc2: change the displayed config name · d7244e4a
      Patrick Delaunay authored
      
      Change the mmc displayed name in U-Boot for stm32_sdmmc2 driver to
      “STM32 SD/MMC”.
      
      This stm32_sdmmc2 driver is for version 2 of the ST HW IP SDMMC but the
      displayed name "STM32 SDMMC2" is confusing for user, between the
      instance of SDMMC and the device identifier of MMC.
      
      For example on EV1 board, we have:
      
      STM32MP1> mmc list
       STM32 SDMMC2: 0 (SD)
       STM32 SDMMC2: 1 (eMMC)
      
      Changed to more clear:
      
      STM32MP1> mmc list
       STM32 SD/MMC: 0 (SD)
       STM32 SD/MMC: 1 (eMMC)
      
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      d7244e4a
    • Patrick Delaunay's avatar
      arm: stm32mp: activate data cache on DDR in SPL · dc7e5f19
      Patrick Delaunay authored
      
      Activate cache on DDR to improve the accesses to DDR used by SPL:
      - CONFIG_SPL_BSS_START_ADDR
      - CONFIG_SYS_SPL_MALLOC_START
      
      Cache is configured only when DDR is fully initialized,
      to avoid speculative access and issue in get_ram_size().
      Data cache is deactivated at the end of SPL, to flush the data cache
      and the TLB.
      
      Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      dc7e5f19
    • Patrick Delaunay's avatar
      arm: stm32mp: activate data cache in SPL and before relocation · 7e8471ca
      Patrick Delaunay authored
      
      Activate the data cache in SPL and in U-Boot before relocation.
      
      In arch_cpu_init(), the function early_enable_caches() sets the early
      TLB, early_tlb[] located .init section, and set cacheable:
      - for SPL, all the SYSRAM
      - for U-Boot, all the DDR
      
      After relocation, the function enable_caches() (called by board_r)
      reconfigures the MMU with new TLB location (reserved in
      board_f.c::reserve_mmu) and re-enable the data cache.
      
      This patch allows to reduce the execution time, particularly
      - for the device tree parsing in U-Boot pre-reloc stage
        (dm_extended_scan_fd =>dm_scan_fdt)
      - in I2C timing computation in SPL (stm32_i2c_choose_solution())
      
      For example, the result on STM32MP157C-DK2 board is:
         1,6s gain for trusted boot chain with TF-A
         2,2s gain for basic boot chain with SPL
      
      For information, as TLB is added in .data section, the binary size
      increased and the SPL load time by ROM code increased (30ms on DK2).
      
      But early malloc can't be used for TLB because arch_cpu_init()
      is executed before the early poll initialization done in spl_common_init()
      called by spl_early_init() So it too late for this use case.
      And if I initialize the MMU and the cache after this function it is
      too late, as dm_init_and_scan and fdt parsing is also called in
      spl_common_init().
      
      And .BSS can be used in board_init_f(): only stack and global can use
      before BSS init done in board_init_r().
      
      So .data is the better solution without hardcoded location but if you
      have size issue for SPL you can deactivate cache for SPL only
      (with CONFIG_SPL_SYS_DCACHE_OFF).
      
      Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      7e8471ca
    • Marek Vasut's avatar
      ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP · 1e444bdc
      Marek Vasut authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      The SPI NOR nWP line is connected to GPIO PF7 on the SoM,
      pull the GPIO line high by default to clear SPI NOR WP.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Patrick Delaunay <patrick.delaunay@st.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Reviewed-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      1e444bdc
    • Marek Vasut's avatar
      ARM: stm32: Define I2C EEPROM bus and address on DHCOM · 8d055b02
      Marek Vasut authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      Define I2C EEPROM bus and address, so that the 'eeprom' command uses
      the correct ones and does not generate the following error:
          eeprom_rw_block: Cannot find udev for a bus 0
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Patrick Delaunay <patrick.delaunay@st.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Reviewed-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      8d055b02
    • Marek Vasut's avatar
      ARM: dts: stm32: Synchronize DDR setttings on DH SoMs · 92ca0f74
      Marek Vasut authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
      into use by the board file instead of the default ones. These new DRAM
      settings are a better fit for the SoMs.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Patrick Delaunay <patrick.delaunay@st.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Reviewed-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      92ca0f74
    • Marek Vasut's avatar
      ARM: dts: stm32: Fix AV96 and DHCOR split · 1ca50174
      Marek Vasut authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      The commit 132e5b68 ("ARM: dts: stm32: Split AV96 into DHCOR SoM
      and AV96 board") was not applied correctly and in full, and omitted
      an important split of the SoM into 3V3 and 1V8 options. The Avenger96
      board is based on the 1V8 IO option of the DHCOR SoM, however this is
      an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM
      regulator to cater for the 96boards 1V8 IO requirements.
      
      Reinstate the split between the 1V8 and 3V3 IO variants.
      
      Fixes: 132e5b68 ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board")
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
      Cc: Patrick Delaunay <patrick.delaunay@st.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Reviewed-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      1ca50174
    • Patrice Chotard's avatar
      stm32mp1: Fix warning display when 1.5A power supply is used · 5eff1684
      Patrice Chotard authored and Patrick Delaunay's avatar Patrick Delaunay committed
      
      On DK1/2 board, when a 1.5A power supply is detected, a warning
      message is displayed. In this message, "1.5mA" is displayed instead
      of "1.5A".
      
      Signed-off-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      Reviewed-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      5eff1684
    • Patrick Delaunay's avatar
      configs: stm32mp1: activate CONFIG_ERRNO_STR · 803e5620
      Patrick Delaunay authored
      
      Add support of errno_str, used in command pmic and regulator.
      
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      Reviewed-by: default avatarPatrice Chotard <patrice.chotard@st.com>
      803e5620
Loading