was written to. It is need on some targets when BAT translation
is enabled.

cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories
Patch by Andreas Engel, 13 Mar 2006

Patch by Stefan Roese, 13 Mar 2006

Patch by Cedric Vincent, 6 June 2005

Patch by Andrew Dyer, 26 Jul 2005

should look at LSB of L1CSRn registers to determine if L1 cache is
enabled, not the MSB.
Patch by Murray Jensen, 19 Jul 2005

Patch by KokHow Teh, 16 Jun 2005

Controller.

 * Debug message can be turned on and off.
 * Waiting for events now times out.
 * Implemented RESET command.
 * Added appropriate nand_bbt_descriptor and nand_oobinfo.

Remaining Problems:
 * Read Status still behaves weird an returns invalid stuff sometimes.
 * ECC Placement does not respect our scheme in nand_oobinfo.

Minimally modified patch by Bluetechnix, Vienna

Patch by Kumar Gala, 10 Feb 2006

done so far:

	* created zylonite board dir (based on lubbock)
	* extended some - but not all pxa sources and headers for Intel
	  Monahans support (CONFIG_CPU_MONAHANS)
	* created Makefile zylonite target + MAKEALL entry
	* added some debug nonsense, remove later, grep for mk@tbd

Status: compiles (eldk-4.0), and can be started with BDI, but runs forever
	and doesn't halt at breakpoints. Hmmm...

Patch by Kumar Gala, 25 Jan 2006

PMC405 and CPCI2DP: Added firmware download and booting via pci.

Patch by Matthias Fuchs, 20 Dec 2005

Patch by Kumar Gala 11 Jan 2006

If its disabled out of reset SW can later enable it if so desired
Patch by Kumar Gala, 11 Jan 2006

Patch by Kumar Gala, 11 Jan 2006

Patch by Kumar Gala, 11 Jan 2006

Patch by Kumar Gala, 11 Jan 2006

The default of 255 is too short for slow devices.
Patch by Martin Nykodym, 12 Dec 2005

No commit message

Simplify TQM85xx Makefile handling.

Patch by Stefan Roese, 29 Nov 2005

Patch by John Otken, 23 Nov 2005

On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.

Patch by Stefan Roese, 27 Nov 2005

- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
  for bank autodetection
Patch by Stefan Roese, 22 Nov 2005

Patch by Stefan Roese, 15 Nov 2005

Patch by Stefan Roese, 07 Nov 2005