- Jan 22, 2020
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Jan 17, 2020
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This is not really a CONFIG since it is not intended to be set by boards. Move it into the compiler header with other similar defines, and rename it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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These CONFIG options are not used anymore. CONFIG_POST_ALT_LIST just causes CONFIG_POST_STD_LIST to be set and it causes tests.c to be compiled. So just make compiling tests.c unconditional. Signed-off-by:
Simon Glass <sjg@chromium.org>
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This seems pretty old now. It has not been converted to driver model and is not used by any boards. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Jan 16, 2020
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The below patch added eSDHC periperhal clock code initially. 2d9ca2c7 mmc: fsl_esdhc: Add peripheral clock support The purpose was to fix up device tree properties "peripheral-frequency" so that linux could get the periperhal clock by it. However the implementation on both u-boot and linux was only for a Freescale SDK release. The linux part implementation had never been upstreamed. These code should not have been exist on u-boot mainline. Let's remove the powerpc part changes but keep the changes in fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized to support SD UHS and eMMC HS200/HS400 speed modes for current Layerscape ARM platforms. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com>
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- Jan 10, 2020
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This target is out of maintenance and can be removed. Signed-off-by:
Holger Brunck <holger.brunck@ch.abb.com> CC: Stefan Roese <sr@denx.de> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com> Reviewed-by:
Stefan Roese <sr@denx.de>
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Tom Rini authored
All platforms currently use the "MCFTMR" DMA timer rather than the PIT timer, so drop the MCFPIT code. Cc: Huan Wang <alison.wang@nxp.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com> Cc: Wolfgang Wegner <w.wegner@astro-kom.de> Signed-off-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Angelo Dureghello <angelo@sysam.it>
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- Jan 07, 2020
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In order to apply an overlay to a DTB. The DTB must have been generated with the option '-@'. Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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enable CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH and get rid of build removal warnings. define CONFIG_GPIO_ENABLE_SPI_FLASH is not longer needed, so remove it from config_whitelist.txt Signed-off-by:
Heiko Schocher <hs@denx.de>
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convert this driver to support DM. Signed-off-by:
Heiko Schocher <hs@denx.de>
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- Dec 23, 2019
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We can use the existing CONFIG_SYS_CONFIG_NAME define for that and remove the option. Also fix the boot string for all km83xx boards. Signed-off-by:
Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
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Remove this from the board header files and move it to Kconfig. Also use the correct default address for kmtegr1. Signed-off-by:
Holger Brunck <holger.brunck@ch.abb.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com> CC: Priyanka Jain <priyanka.jain@nxp.com> CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
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- Dec 15, 2019
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When device-tree compilation fails it is sometimes tricky to see which line is broken, since the input file to dtc is a pre-processed version of the device tree. Add a line that points to the file that needs to be checked: When the error is in the main .dts file, output is something like this: output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47 syntax error FATAL ERROR: Unable to parse input tree but in fact looking at that file shows nothing useful: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) Instead we need to look at the preprocessed file, which shows: 163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1) Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is not being resolved by the preprocessor. This commit adds an additional useful message: Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors Note that if the error is reported in an included file, such as u-boot.dtsi then the output is the following: Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error FATAL ERROR: Unable to parse input tree But again, if the error is due to a preprocessor failure, like this: filename = CONFIG_IFW_INPUT_FILE; then you can't tell what the problem is by looking at the source. All you see is the original code: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; }; intel-fsp-m { filename = CONFIG_FSP_FILE_M; }; Everything looks fine. But looking at the output of the preprocessor: intel-ifwi { filename = CONFIG_IFW_INPUT_FILE; ... }; intel-fsp-m { filename = "fsp_m.bin"; }; This shows that the filename (normally "fitimage.bin") has not been inserted the preprocess, leading to the realisation that the value should be CONFIG_IFWI_INPUT_FILE. If the above does not make sense, I encourage people to try introducing errors in the device tree preprocessed values. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass is included in SPL/TPL without any control for boards. Some boards may want to disable this to reduce code size where GPIOs are not needed in SPL or TPL. Add a new Kconfig option to permit this. Default it to 'y' so that existing boards work correctly. Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to preserve the current behaviour. Also update the 74x164 GPIO driver since it cannot build with SPL. This allows us to remove the hacks in config_uncmd_spl.h and Makefile.uncmd_spl (eventually those files should be removed). Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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- Dec 06, 2019
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Imported from linux kernel v5.3: pkcs7.asn1 without changes pkcs7.h with changes marked as __UBOOT__ pkcs7_parser.h without changes pkcs7_parser.c with changes marked as __UBOOT__ Signed-off-by:
AKASHI Takahiro <takahiro.akashi@linaro.org>
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Imported from linux kernel v5.3: build_OID_registry without changes oid_registry.h without changes oid_registry.c with changes marked as __UBOOT__ Signed-off-by:
AKASHI Takahiro <takahiro.akashi@linaro.org>
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This rule will be used to build x509 and pkcs7 parsers. Signed-off-by:
AKASHI Takahiro <takahiro.akashi@linaro.org>
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Imported from linux kernel v5.3: asn1.h without changes asn1_ber_bytecode.h without changes asn1_decoder.h without changes asn1_compiler.c without changes This host command will be used to create a ASN1 parser, for example, for pkcs7 messages or x509 certificates. More specifically, it will generate *byte code* which will be interpreted by asn1 decoder library. Signed-off-by:
AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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- Dec 04, 2019
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Dec 03, 2019
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Tom Rini authored
This converts the following to Kconfig: CONFIG_SYS_CORTINA_FW_IN_MMC CONFIG_SYS_CORTINA_FW_IN_NAND CONFIG_SYS_CORTINA_FW_IN_NOR CONFIG_SYS_CORTINA_FW_IN_REMOTE CONFIG_SYS_CORTINA_FW_IN_SPIFLASH Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Dec 02, 2019
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This feature is not enabled by any board. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Nov 23, 2019
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Add __pycache__ to ignored files and extend the rule for _libfdt to also include generated shared objects (e.g. _libfdt.cpython-37m-x86_64-linux-gnu.so). Signed-off-by:
Bartosz Golaszewski <bgolaszewski@baylibre.com>
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The 'debug' and 'printf' functions were previously added to the list of logFunctions in commit 0cab4211 ("checkpatch.pl: Add 'debug' to the list of logFunctions") and commit 397bfd46 ("checkpatch.pl: Add 'printf' to logFunctions") but these additions were lost when newer versions of checkpatch were pulled in from the upstream Linux kernel version. This restores them so that you don't end up in a situation where checkpatch will give a warning for "quoted string split across lines" which you cannot fix without getting a warning for "line over 80 characters" instead. Signed-off-by:
James Byrne <james.byrne@origamienergy.com>
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- Nov 21, 2019
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Nov 20, 2019
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Tom Rini authored
- In ARMv8 NXP Layerscape platforms we also need to make use of CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so. - On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define to 0. - Add Kconfig entry for ENV_ADDR. - Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it. - Add ENV_xxx_REDUND options that depend on their primary option and SYS_REDUNDAND_ENVIRONMENT - On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR for the pre-main-U-Boot environment location. - On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but rather it being non-zero, as it will now be zero by default. - Rework the env_offset absolute in env/embedded.o to not use CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within ENV_IS_IN_FLASH. - Migrate all platforms. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: uboot-stm32@st-md-mailman.stormreply.com Signed-off-by:
Tom Rini <trini@konsulko.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
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Tom Rini authored
We have CONFIG_ENV_SIZE_IS_REDUND but don't really use it. We have one board where we can simply multiple CONFIG_ENV_SIZE by two for the same result. The other place where we could but were not previously using this is for where env_internal.h checks for if we should set ENV_IS_EMBEDDED. This seems like the most likely use, historically, of the variable, but it was not used. Add logic to check for this now. Cc: Wolfgang Denk <wd@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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- Nov 17, 2019
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Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all cases, making the TPL bigger. There may be cases where the TPL is really size constrained due to its underlying ram size. Therefore introduce a new TPL_FRAMEWORK option and make the relevant conditionals check for both. The default is set to "y if SPL_FRAMEWORK" to mimic the previous behaviour where the TPL would always get the SPL framework if it was enabled in SPL. Signed-off-by:
Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com>
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- Nov 12, 2019
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Tom Rini authored
Move this symbol to Kconfig. As part of this we can drop a UBI-specific symbol that was a stop-gap for not having this particular symbol in Kconfig. Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Nov 07, 2019
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:
Tom Rini <trini@konsulko.com>
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- Nov 06, 2019
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Vignesh Raghavendra authored
Add support for USB3 host and gadget driver. This is a direct sync of Linux kernel Cadence USB stack that from v5.4-rc1 release. Driver has been modified so that it compiles without errors against U-Boot code base. Features not required for U-Boot such as scatter-gather DMA and OTG interrupt handling has been dropped. Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> [jjhiblot@ti.com: Add PHY support] Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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- Nov 05, 2019
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Simon Glass authored
This function should use a void * type, not char *. This causes an error: TypeError: in method 'fdt_property_stub', argument 3 of type 'char const *' Fix it. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Sync up the libfdt Python bindings with upstream, commit: 430419c (tests: fix some python warnings) Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Build this swig module with Python 3. Signed-off-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
Bring over the fdt from this commit: 430419c (origin/master) tests: fix some python warnings adding in the 'assumptions' series designed to reduce code size. Signed-off-by:
Simon Glass <sjg@chromium.org>
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- Oct 31, 2019
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Update from upstream. Just minor changes like checking that the author has also done a sign-off. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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- Oct 15, 2019
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Signed-off-by:
Giulio Benetti <giulio.benetti@benettiengineering.com>
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The commit "libfdt: fdt_address_cells() and fdt_size_cells()" introduced a bug as it consolidated code between the helpers for getting be 0, and is frequently found so in practice for /cpus. IEEE1275 only requires implementations to handle 1..4 for #address-cells, although one could make a case for #address-cells == #size-cells == 0 being used to represent a bridge with a single port. While we're there, it's not totally obvious that the existing implicit cast of a u32 to int will give the correct results according to strict C, although it does work in practice. Straighten that up to cast only after we've made our range checks. This is based on upstream commit: b8d6eca ("libfdt: Allow #size-cells of 0") but misses the test cases,as we don't implement them in U-Boot. Signed-off-by:
Matthias Brugger <mbrugger@suse.com>
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According to the device tree specification, the default value for was not present. This patch also makes fdt_address_cells() and fdt_size_cells() conform to the behaviour documented in libfdt.h. The defaults are only returned if fdt_getprop() returns -FDT_ERR_NOTFOUND, otherwise the actual error is returned. This is based on upstream commit: aa7254d ("libfdt: return correct value if #size-cells property is not present") but misses the test case part, as we don't implement them in U-Boot. Signed-off-by:
Matthias Brugger <mbrugger@suse.com>
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Add internal fdt_cells() to avoid copy and paste. Fix typo in fdt_size_cells() documentation comment. This is based in upstream commit: c12b2b0 ("libfdt: fdt_address_cells() and fdt_size_cells()") but misses the test cases, as we don't implement them in U-Boot. Signed-off-by:
Matthias Brugger <mbrugger@suse.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Simon Glass authored
At present these two sections of code are linked together into a single 2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware Interface Table) in the ROM and the pointer for this needs to go at 0xffffffc0 which is in the middle of these two sections. Make use of the new 'reset' entry and change the existing 16-bit entry to include just the 16-bit data. Signed-off-by:
Simon Glass <sjg@chromium.org>
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