- Apr 16, 2020
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This file is potentially useful to other architectures saddled with ACPI so move most of its contents to a common location. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
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This header relates to ACPI and we are about to add some more ACPI headers. Move this one into a new directory so they are together. The header inclusion in pci_rom.c is not specific to x86 anymore, so drop the #ifdef CONFIG_X86. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> -
Add a sandbox test for the basic ACPI functionality we have so far. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Add this binding from Linux v5.4. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
ACPI (Advanced Configuration and Power Interface) is a standard for specifying information about a platform. It is a little like device tree but the bindings are part of the specification and it supports an interpreted bytecode language. Driver model does not use ACPI for U-Boot's configuration, but it is convenient to have it support generation of ACPI tables for passing to Linux, etc. As a starting point, add an optional set of ACPI operations to each device. Initially only a single operation is available, to obtain the ACPI name for the device. More operations are added later. Enable ACPI for sandbox to ensure build coverage and so that we can add tests. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Add the C version of this header. It includes a few Chrome OS bits which are disabled for a normal build. Signed-off-by:
Wolfgang Wallner <wolgang.wallner@br-automation.com>
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At present if reading a BAR returns 0xffffffff then the value is masked and a different value is returned. This makes it harder to detect the problem when debugging. Update the function to avoid masking in this case. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
With P2SB the initial BAR (base-address register) is set up by TPL and this is used unchanged right through U-Boot. At present the reading of this address is split between the ofdata() and probe() methods. There are a few problems that are unique to the p2sb. One is that its children need to call pcr_read32(), etc. which needs to have the p2sb address correct. Also some of its children are pinctrl devices and pinctrl is used when any device is probed. So p2sb really needs to get its base address set up in ofdata_to_platdata(), before it is probed. Another point is that reading the p2sb BAR will not work if the p2sb is hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI enumeration. Reading ofdata in ofdata_to_platdata() is the correct place anyway, so this is easy to fix. Move the code into one place and use the early-regs property in all cases for simplicity and to avoid needing to probe any PCI devices just to read the BAR. Signed-off-by:
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Some files are taken or modified from coreboot, but the files are no-longer part of the coreboot project. Fix the wording in a few places. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Add a means to avoid configuring a device when needed. Add an explanation of why this is useful to the binding file. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
At present the cleanup() method is called on every transfer. It should only be called on failing transfers. Fix this and tidy up the error handling a little. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
This device should use ready-gpios rather than ready-gpio. Fix it. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Add a comment for the private structure Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
At present the cr50 driver claims the locality and does not release it for Linux. This causes problems. Fix this by tracking what is claimed, and adding a 'remove' method. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
With ACPI we need to describe the settings of the SPI bus. Add enums to handle this. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: -
Different CPUs may support different address widths, meaning the amount of memory they can address. Add a property for this to the cpu_info struct. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
SPCR has no clue if the UART base clock speed is different to the default one. However, the SPCR 1.04 defines baud rate 0 as a preconfigured state of UART and OS is supposed not to touch the configuration of the serial device. Linux kernel supports that starting from v5.0, see commit b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state") for the details. Signed-off-by:Bin Meng <bmeng.cn@gmail.com> -
Some callers may need the UART base clock speed value. Provide it in the ->getinfo() callback. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> -
Some callers of serial_getinfo() would like to know the UART base clock speed in order to make decision what to pass to OS in some cases. In particular, ACPI SPCR table expects only certain base clock speed and thus we have to act accordingly. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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- Apr 15, 2020
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https://gitlab.denx.de/u-boot/custodians/u-boot-stmTom Rini authored
- Replace STM32MP1_TRUSTED by TFABOOT flag - Enable bootd, iminfo, imxtract on ST defconfig - Rename LEDs to match silkscreen on AV96 - Add KS8851-16MLL ethernet on FMC2 - Define FMC2 base address - net: dwc_eth_qos: implement reset-gpios for stm32 - net: dwc_eth_qos: implement phy reg and max-speed for stm32
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git://git.denx.de/u-boot-marvellTom Rini authored
- Common: honour hw_margin_ms property (Rasmus) - sp805_wdt: get platform clock from dt (Rayagonda)
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Use the correct macro to test presence CONFIG_LED: replace CONFIG_IS_ENABLED(CONFIG_LED) by CONFIG_IS_ENABLED(LED) Issue see during review unrelated patch "board: stm32mp1: update management of boot-led" http://patchwork.ozlabs.org/patch/1264823/ Cc: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
Marek Vasut <marex@denx.de> Reviewed-by:
Patrice Chotard <patrice.chotard@st.com>
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Enable these standard U-Boot commands for image manipulation and for starting the default boot command using 'boot' command in U-Boot shell. Cc: Marek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: -
The LED labels do not match the silkscreen on the board, fix it. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT introduced by the commit 535d76a1 ("armv8: layerscape: Add TFABOOT support"). This config CONFIG_TFABOOT is activated for the trusted boot chain, when U-Boot is loaded by TF-A. Signed-off-by:
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Add DT entries, Kconfig entries and board-specific entries to configure FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot. Signed-off-by:
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Define FMC2 base address, for use in board files, until there is an actual FMC2 bus driver. Signed-off-by:
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Add management of property "reg" to configure @ of phy and also "max-speed" property to specify maximum speed in Mbit/s supported by the device Signed-off-by:
Christophe Roullier <christophe.roullier@st.com> Reviewed-by:
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Add management of property "reset-gpios" in the node identified by "phy-handle" to configure any GPIO used to reset the PHY. Signed-off-by:
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Get the watchdog platform clock from the DTS file using clk subsystem and use the same for calculating ticks in msec. Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by:
Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com> Reviewed-by:
Stefan Roese <sr@denx.de>
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Some watchdog devices, e.g. external gpio-triggered ones, must be reset more often than once per second, which means that the current rate-limiting logic in watchdog_reset() fails to keep the board alive. gpio-wdt.txt in the linux source tree defines a "hw_margin_ms" property used to specifiy the maximum time allowed between resetting the device. Allow any watchdog device to specify such a property, and then use a reset period of one quarter of that. We keep the current default of resetting once every 1000ms. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by:
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This function is a bit large for an inline function, and for U-Boot proper, it is called via a function pointer anyway (in board_r.c), so cannot be inlined. It will shortly set a global variable to be used by the watchdog_reset() function in wdt-uclass.c, so this also allows making that variable local to wdt-uclass.c. The WATCHDOG_TIMEOUT_SECS define is not used elsewhere. Signed-off-by:
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Since WATCHDOG_TIMEOUT_MSECS was converted to Kconfig (commit ca51ef7c), CONFIG_WATCHDOG_TIMEOUT_MSECS has been guaranteed to be defined. So remove the dead fallback ifdeffery. Signed-off-by:
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- Apr 14, 2020
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git://git.denx.de/u-boot-marvellTom Rini authored
- Misc enhancements to Clearfog, including board variant detection (Joel) - Misc enhancements to Turris Mox, including generalization of the ARMADA37xx DDR size detection (Marek)
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Use the new a3700_fdt_fix_pcie_regions function in turris_mox.c so that MOX boards with 4 GB RAM are fully supported. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
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In case when ARM Trusted Firmware changes the default address of PCIe regions (which can be done for devices with 4 GB RAM to maximize the amount of RAM the device can use) we add code that looks at how ATF changed the PCIe windows in the CPU Address Decoder and changes given device-tree blob accordingly. Signed-off-by:
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In order to support MOX boards with 2 GB or 4 GB RAM, we use the new Armada-3700 generic code for memory information structures. This is done by removing dram_init and dram_init_banksize from turris_mox.c, in order for the generic, weak definitions to be used. Also for boards with 4 GB RAM it is needed to increase CONFIG_NR_DRAM_BANKS to 2 in turris_mox_defconfig. Signed-off-by:
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Currently on Armada-37xx the mem_map structure is statically defined to map first 2 GB of memory as RAM region, and system registers and PCIe region device region. This is insufficient for when there is more RAM or when for example the PCIe windows is mapped to another address by the CPU Address Decoder. In the case when the board has 4 GB RAM, on some boards the ARM Trusted Firmware can move the PCIe window to another address, in order to maximize possible usable RAM. Also the dram_init and dram_init_banksize looks for information in device-tree, and therefore different device trees are needed for boards with different RAM sizes. Therefore we add code that looks at how the ARM Trusted Firmware has configured the CPU Address Decoder windows, and then we update the mem_map structure and compute gd->ram_size and gd->bd->bi_dram bank base addresses and sizes accordingly. Signed-off-by:
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Move Armada-8k specific DRAM init code into armada-8k specific directory. Signed-off-by:
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Sort #includes alphabetically, the only exception is common.h, which is included first in most parts of U-Boot. Signed-off-by:
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