As the driver of on-chip reset controller became available
we are ready to enable it.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Force inlining of IOC related functions used in other cache
functions. This is preventive change.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Since version 3.0 ARC HS supports SL$ (L2 system level cache)
disable. So add support for SL$ disable/enable to code.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

- Provide serial base clock speed via getinfo() for ACPI SPCR
- Initial ACPI support from DM core by leveraging existing ACPI support
  in x86

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Since ut_asserteq_mem() uses bin2hex() we should include this header in
ut.h to avoid errors. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

The DMA Remapping Reporting (DMAR) table contains information about DMA
remapping.

Add a version simple version of this table with only the minimum fields
filled out. i.e. no entries.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Each ACPI table has its own version number. Add the version numbers in a
single function so we can keep them consistent and easily see what
versions are supported.

Start a new acpi_table file in a generic directory to house this function.
We can move things over to this file from x86 as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

The ASL compiler cannot handle C structures and the like so needs some
sort of header guard around these.

We already have an __ASSEMBLY__ #define but it seems best to create a new
one for ACPI since the rules may be different.

Add the check to a few files that ACPI always includes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

This file is potentially useful to other architectures saddled with ACPI
so move most of its contents to a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

This header relates to ACPI and we are about to add some more ACPI
headers. Move this one into a new directory so they are together.

The header inclusion in pci_rom.c is not specific to x86 anymore, so drop
the #ifdef CONFIG_X86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add a sandbox test for the basic ACPI functionality we have so far.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add this binding from Linux v5.4.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

ACPI (Advanced Configuration and Power Interface) is a standard for
specifying information about a platform. It is a little like device
tree but the bindings are part of the specification and it supports an
interpreted bytecode language.

Driver model does not use ACPI for U-Boot's configuration, but it is
convenient to have it support generation of ACPI tables for passing to
Linux, etc.

As a starting point, add an optional set of ACPI operations to each
device. Initially only a single operation is available, to obtain the
ACPI name for the device. More operations are added later.

Enable ACPI for sandbox to ensure build coverage and so that we can add
tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add the C version of this header. It includes a few Chrome OS bits which
are disabled for a normal build.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present if reading a BAR returns 0xffffffff then the value is masked
and a different value is returned. This makes it harder to detect the
problem when debugging.

Update the function to avoid masking in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

With P2SB the initial BAR (base-address register) is set up by TPL and
this is used unchanged right through U-Boot.

At present the reading of this address is split between the ofdata() and
probe() methods. There are a few problems that are unique to the p2sb.
One is that its children need to call pcr_read32(), etc. which needs to
have the p2sb address correct. Also some of its children are pinctrl
devices and pinctrl is used when any device is probed. So p2sb really
needs to get its base address set up in ofdata_to_platdata(), before it is
probed.

Another point is that reading the p2sb BAR will not work if the p2sb is
hidden. The FSP-S seems to hide it, presumably to avoid confusing PCI
enumeration.

Reading ofdata in ofdata_to_platdata() is the correct place anyway, so
this is easy to fix.

Move the code into one place and use the early-regs property in all cases
for simplicity and to avoid needing to probe any PCI devices just to read
the BAR.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Some files are taken or modified from coreboot, but the files are
no-longer part of the coreboot project. Fix the wording in a few places.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add a means to avoid configuring a device when needed. Add an explanation
of why this is useful to the binding file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present the cleanup() method is called on every transfer. It should
only be called on failing transfers. Fix this and tidy up the error
handling a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

This device should use ready-gpios rather than ready-gpio. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add a comment for the private structure

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present the cr50 driver claims the locality and does not release it for
Linux. This causes problems. Fix this by tracking what is claimed, and
adding a 'remove' method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

With ACPI we need to describe the settings of the SPI bus. Add enums to
handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Different CPUs may support different address widths, meaning the amount of
memory they can address. Add a property for this to the cpu_info struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Andy Shevchenko authored 5 years ago and Bin Meng committed 4 years ago

SPCR has no clue if the UART base clock speed is different to
the default one. However, the SPCR 1.04 defines baud rate 0 as
a preconfigured state of UART and OS is supposed not to touch
the configuration of the serial device.

Linux kernel supports that starting from v5.0, see commit
b413b1abeb21 ("ACPI: SPCR: Consider baud rate 0 as preconfigured state")
for the details.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Andy Shevchenko authored 5 years ago and Bin Meng committed 4 years ago

Some callers may need the UART base clock speed value.
Provide it in the ->getinfo() callback.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Andy Shevchenko authored 5 years ago and Bin Meng committed 4 years ago

Some callers of serial_getinfo() would like to know the UART base
clock speed in order to make decision what to pass to OS in some
cases. In particular, ACPI SPCR table expects only certain base
clock speed and thus we have to act accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

- Replace STM32MP1_TRUSTED by TFABOOT flag
- Enable bootd, iminfo, imxtract on ST defconfig
- Rename LEDs to match silkscreen on AV96
- Add KS8851-16MLL ethernet on FMC2
- Define FMC2 base address
- net: dwc_eth_qos: implement reset-gpios for stm32
- net: dwc_eth_qos: implement phy reg and max-speed for stm32

- Common: honour hw_margin_ms property (Rasmus)
- sp805_wdt: get platform clock from dt (Rayagonda)

Patrick Delaunay authored 4 years ago and Patrice Chotard committed 4 years ago

Use the correct macro to test presence CONFIG_LED:
replace CONFIG_IS_ENABLED(CONFIG_LED) by CONFIG_IS_ENABLED(LED)

Issue see during review unrelated patch
"board: stm32mp1: update management of boot-led"
http://patchwork.ozlabs.org/patch/1264823/



Cc: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

Patrick Delaunay authored 4 years ago and Patrice Chotard committed 4 years ago

Enable these standard U-Boot commands for image manipulation and for
starting the default boot command using 'boot' command in U-Boot shell.

Cc: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Marek Vasut authored 4 years ago and Patrice Chotard committed 4 years ago

The LED labels do not match the silkscreen on the board, fix it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Patrick Delaunay authored 4 years ago and Patrice Chotard committed 4 years ago

Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp
specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT
introduced by the commit 535d76a1 ("armv8: layerscape: Add TFABOOT
support").
This config CONFIG_TFABOOT is activated for the trusted boot chain,
when U-Boot is loaded by TF-A.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

Marek Vasut authored 4 years ago and Patrice Chotard committed 4 years ago

Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Marek Vasut authored 4 years ago and Patrice Chotard committed 4 years ago

Define FMC2 base address, for use in board files, until there is an
actual FMC2 bus driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>

Patrick Delaunay authored 5 years ago and Patrice Chotard committed 4 years ago

Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Christophe Roullier authored 5 years ago and Patrice Chotard committed 4 years ago

Add management of property "reset-gpios" in the node identified by
"phy-handle" to configure any GPIO used to reset the PHY.

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Rayagonda Kokatanur authored 4 years ago and Stefan Roese committed 4 years ago

Get the watchdog platform clock from the DTS file
using clk subsystem and use the same for calculating
ticks in msec.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Rasmus Villemoes authored 5 years ago and Stefan Roese committed 4 years ago

Some watchdog devices, e.g. external gpio-triggered ones, must be
reset more often than once per second, which means that the current
rate-limiting logic in watchdog_reset() fails to keep the board alive.

gpio-wdt.txt in the linux source tree defines a "hw_margin_ms"
property used to specifiy the maximum time allowed between resetting
the device. Allow any watchdog device to specify such a property, and
then use a reset period of one quarter of that. We keep the current
default of resetting once every 1000ms.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>

Rasmus Villemoes authored 5 years ago and Stefan Roese committed 4 years ago

This function is a bit large for an inline function, and for U-Boot
proper, it is called via a function pointer anyway (in board_r.c), so
cannot be inlined.

It will shortly set a global variable to be used by the
watchdog_reset() function in wdt-uclass.c, so this also allows making
that variable local to wdt-uclass.c.

The WATCHDOG_TIMEOUT_SECS define is not used elsewhere.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>