Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

This header relates to ACPI and we are about to add some more ACPI
headers. Move this one into a new directory so they are together.

The header inclusion in pci_rom.c is not specific to x86 anymore, so drop
the #ifdef CONFIG_X86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

ACPI (Advanced Configuration and Power Interface) is a standard for
specifying information about a platform. It is a little like device
tree but the bindings are part of the specification and it supports an
interpreted bytecode language.

Driver model does not use ACPI for U-Boot's configuration, but it is
convenient to have it support generation of ACPI tables for passing to
Linux, etc.

As a starting point, add an optional set of ACPI operations to each
device. Initially only a single operation is available, to obtain the
ACPI name for the device. More operations are added later.

Enable ACPI for sandbox to ensure build coverage and so that we can add
tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present if reading a BAR returns 0xffffffff then the value is masked
and a different value is returned. This makes it harder to detect the
problem when debugging.

Update the function to avoid masking in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add a means to avoid configuring a device when needed. Add an explanation
of why this is useful to the binding file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present the cleanup() method is called on every transfer. It should
only be called on failing transfers. Fix this and tidy up the error
handling a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

This device should use ready-gpios rather than ready-gpio. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Add a comment for the private structure

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

At present the cr50 driver claims the locality and does not release it for
Linux. This causes problems. Fix this by tracking what is claimed, and
adding a 'remove' method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Simon Glass authored 4 years ago and Bin Meng committed 4 years ago

Different CPUs may support different address widths, meaning the amount of
memory they can address. Add a property for this to the cpu_info struct.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Andy Shevchenko authored 5 years ago and Bin Meng committed 4 years ago

Some callers may need the UART base clock speed value.
Provide it in the ->getinfo() callback.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Andy Shevchenko authored 5 years ago and Bin Meng committed 4 years ago

Some callers of serial_getinfo() would like to know the UART base
clock speed in order to make decision what to pass to OS in some
cases. In particular, ACPI SPCR table expects only certain base
clock speed and thus we have to act accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Patrick Delaunay authored 4 years ago and Patrice Chotard committed 4 years ago

Activate ARCH_SUPPORT_TFABOOT and replace the arch stm32mp
specific config CONFIG_STM32MP1_TRUSTED by the generic CONFIG_TFABOOT
introduced by the commit 535d76a1 ("armv8: layerscape: Add TFABOOT
support").
This config CONFIG_TFABOOT is activated for the trusted boot chain,
when U-Boot is loaded by TF-A.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

Patrick Delaunay authored 5 years ago and Patrice Chotard committed 4 years ago

Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Christophe Roullier authored 5 years ago and Patrice Chotard committed 4 years ago

Add management of property "reset-gpios" in the node identified by
"phy-handle" to configure any GPIO used to reset the PHY.

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrice CHOTARD <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

Rayagonda Kokatanur authored 4 years ago and Stefan Roese committed 4 years ago

Get the watchdog platform clock from the DTS file
using clk subsystem and use the same for calculating
ticks in msec.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Reviewed-by: Stefan Roese <sr@denx.de>

Rasmus Villemoes authored 5 years ago and Stefan Roese committed 4 years ago

Some watchdog devices, e.g. external gpio-triggered ones, must be
reset more often than once per second, which means that the current
rate-limiting logic in watchdog_reset() fails to keep the board alive.

gpio-wdt.txt in the linux source tree defines a "hw_margin_ms"
property used to specifiy the maximum time allowed between resetting
the device. Allow any watchdog device to specify such a property, and
then use a reset period of one quarter of that. We keep the current
default of resetting once every 1000ms.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>

Rasmus Villemoes authored 5 years ago and Stefan Roese committed 4 years ago

This function is a bit large for an inline function, and for U-Boot
proper, it is called via a function pointer anyway (in board_r.c), so
cannot be inlined.

It will shortly set a global variable to be used by the
watchdog_reset() function in wdt-uclass.c, so this also allows making
that variable local to wdt-uclass.c.

The WATCHDOG_TIMEOUT_SECS define is not used elsewhere.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>

Heinrich Schuchardt authored 5 years ago and Stefan Roese committed 4 years ago

The value of local variable ecc is immediately overwritten. So we can
remove the first assignment.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

Chris Packham authored 5 years ago and Stefan Roese committed 4 years ago

For some layouts it is necessary to adjust the CK_DELAY parameter to
successfully complete DDR training. Add the ability to specify the
CK_DELAY in the mv_ddr_topology_map.

Signed-off-by: Chris Packham <judge.packham@gmail.com>

Base driver for Broadcom xHCI controllers

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>

Use ofnode_ instead of fdt_ APIs so that the drivers can support live DT.
This patch updates usb_get_dr_mode() and usb_get_maximum_speed() to use
ofnode as parameter instead of fdt offset. And all the drivers who use
these APIs update to use live dt APIs at the same time.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Use dev_read_addr_ptr() instead of devfdt_get_addr() so that we can support
live DT.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>

The fdtdec.h is no use in this file, remove the include code.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

Bin Meng authored 4 years ago and Tom Rini committed 4 years ago

When building with gcc 9.2.0, the following build warning was seen:

  drivers/video/sunxi/sunxi_display.c: In function 'video_hw_init':
  drivers/video/sunxi/sunxi_display.c:1217:2:
    error: '%s' directive argument is null [-Werror=format-overflow=]

Change sunxi_get_mon_desc() to not return NULL for the default case,
to fix the compiler warning.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Biwen Li authored 4 years ago and Priyanka Jain committed 4 years ago

This reverts commit 2a5d5d27.
The commit breaks uboot boot (hang in ddr init)
on many PowerPC boards like P3041DS, P4080DS

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>

Ovidiu Panait authored 4 years ago and Simon Glass committed 4 years ago

Refactor the printing sequence in dm_dump_drivers to make it more clear.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

Ovidiu Panait authored 4 years ago and Simon Glass committed 4 years ago

Currently, dm drivers command produces a segfault:
=> dm drivers
Driver                Compatible
--------------------------------
Segmentation fault (core dumped)

This is caused by a NULL pointer dereference of entry->of_match.
Add a check to prevent this.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>

Marek Vasut authored 4 years ago and Tom Rini committed 4 years ago

Rather than keeping the asynchronous schedule running always, keep it
running only across USB mass storage transfers for now, as it seems
that keeping it running all the time interferes with certain control
transfers during device enumeration.

Note that running the async schedule all the time should not be an
issue, especially on EHCI HCD, as that one implements most of the
transfers using async schedule.

Note that we have usb_disable_asynch(), which however is utterly broken.
The usb_disable_asynch() blocks the USB core from doing async transfers
by setting a global flag. The async schedule should however be disabled
per USB controller. Moreover, setting a global flag does not prevent the
controller from using the async schedule, which e.g. the EHCI HCD does.

This patch implements additional callback to the controller, which
permits it to lock the async schedule and keep it running across
multiple transfers. Once the schedule is unlocked, it must also be
disabled. This thus prevents the async schedule from running outside
of the USB mass storage transfers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Tom Rini <trini@konsulko.com> [omap3_beagle, previously failing]

Sean Anderson authored 4 years ago and Tom Rini committed 4 years ago

Add a test for the dm drivers command. Also fix a null pointer dereference
revealed by said test.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

The commit a6730255 ("serial: zynq: Initialize uart only before
relocation") introduced code which detects relocation which is working for
single uart instance. With multiple instances in place there is a need to
enable and setup every instance. That's why detect if TX is enabled. If it
is then don't initialize uart again.
In post probe setbrg is called to setup baudrate but values should be the
same.

As a side effect of this change is that DECLARE_GLOBAL_DATA_PTR can be
removed completely.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add support for Xilinx window watchdog, which can be found on
Versal platforms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Reviewed-by: Stefan Roese <sr@denx.de>

U-Boot proper can still run in EL3 without using firmware interface wired
via ATF. For supporting this use case there is a need to check EL level
where U-Boot runs and based on that choose the way how to talk to firmware.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

gd is not used in the driver that's why declaration is not needed at all.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Not all IPs have private MDIO bus and MDIO bus should be shared between
several IPs. In past one patch tried to implement it
(https://lists.denx.de/pipermail/u-boot/2018-February/319285.html

)
in pretty raw way but it is not the cleanest solution.
This patch is just taking the part of that solution to be able to handle it
over releases without conflicts.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

There is no reason to continue when DT status property indicates that NAND
flash is disabled. But that means that NOR flash should be present that's
why try it find it out.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

xnand structure is private data structure and it is handled by core and
probe shouldn't touch it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Add cache flush to zynq_gem_free_pkt. This is necessary
because some net routines would modify this buffer in place.
The cache_invalidate in the zynq_gem_recv function would cause
the modifications to the buffer to overwrite the DMA from the GEM,
if cache coherency is not enabled in the GEM, the next time the
buffer is in use.

Flushing the cache when the buffer is no longer in use by the
net functions ensures that the GEM DMA is going to take place
into a clean buffer.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Until now, the mmc clock was left in a good enough state by the ROM
code to be used by the controller. However on some SoC, if the ROM
code finds a bootloader on USB or SPI, it might leave the MMC clock
in state the controller cannot work with.

Enable the input clocks provided to the mmc controller. While the
u-boot mmc controller driver is not doing fancy settings like the Linux,
it at least needs to make these clocks are running.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Add missing break for CLKID_PCIE_PLL in switch statement.

Reported by CppCheck.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Fixes: 08e09c26 ("clk: meson-g12a: Add PCIE PLL support")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>