- Nov 09, 2021
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Minkyu Kang authored
to fix following checkpatch warings. WARNING: struct should normally be const Signed-off-by:
Minkyu Kang <mk7.kang@samsung.com> Cc: Dzmitry Sankouski <dsankouski@gmail.com> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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At present the counter never hits the comparitor in this case. Add a special case. This ensures that the snow backlight works when at full brightness. Fixes: 76c2ff3e video: backlight: fix pwm's duty cycle calculation Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
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- Nov 07, 2021
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Heinrich Schuchardt authored
Currently output of dfu commands ends on a line with leading hash signs ('#'). The succeeding output should be placed on a new line. After writing updates via dfu print a new line. Signed-off-by:Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
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The current EFI video driver only works when running in the stub. In that case the stub calls boot services (before jumping to U-Boot proper) and copies the graphics info over to the efi table. This is necessary because the stub exits boot services before jumping to U-Boot. The app maintains access to boot services throughout its life, so does not need to do this. Update the driver to support calling boot services directly. Enable video output for the app. Note that this uses the EFI_GRAPHICS_OUTPUT_PROTOCOL protocol, even though it mentions vesa. A sample qemu command-line for this case is: qemu-system-x86_64 -bios /usr/share/edk2.git/ovmf-ia32/OVMF-pure-efi.fd -drive id=disk,file=try.img,if=none,format=raw -nic none -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0 Signed-off-by:
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- Nov 05, 2021
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Tom Rini authored
This converts the following to Kconfig: CONFIG_SPL_DRIVERS_MISC CONFIG_SPL_ENV_SUPPORT CONFIG_SPL_GPIO CONFIG_SPL_I2C CONFIG_SPL_LDSCRIPT CONFIG_SPL_LIBCOMMON_SUPPORT CONFIG_SPL_LIBGENERIC_SUPPORT CONFIG_SPL_LOAD_FIT_ADDRESS CONFIG_SPL_MMC CONFIG_SPL_NAND_SUPPORT CONFIG_SPL_NO_CPU_SUPPORT CONFIG_SPL_OS_BOOT CONFIG_SPL_POWER CONFIG_SPL_STACK_R CONFIG_SPL_STACK_R_ADDR CONFIG_SPL_WATCHDOG CONFIG_SPL_TEXT_BASE Signed-off-by:Tom Rini <trini@konsulko.com>
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- Nov 04, 2021
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Add an option to automatically register watchdog devices with the wdt_reboot driver for use with sysreset. This allows sysreset to be a drop-in replacement for platform-specific watchdog reset code, without needing any device tree changes. Signed-off-by:
Samuel Holland <samuel@sholland.org> Reviewed-by:
Stefan Roese <sr@denx.de>
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Currently, the wdt_reboot driver always gets its watchdog device reference from an OF node. This prevents selecting a watchdog at runtime. Move the watchdog device reference to the plat data, so the driver can be bound with the reference pre-provided. The reference will still be acquired from the OF node if it is not already provided. Reviewed-by:
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These driver probe functions are not (and should not be) called from outside the respective driver source files. Therefore, the functions should be marked static. Reviewed-by:
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None of the sysreset drivers do anything beyond providing sysreset uclass ops. They should depend on the sysreset uclass. Reviewed-by:
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- Nov 03, 2021
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When allocate the GPD ring, and tell its address to the controller, then the driver starts or resumes the QMU, the controller will try to access the first GPD, so need flush the first one to avoid wrong GPD status. Reported-by:
Xin Lin <Xin.Lin@mediatek.com> Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com>
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According to the Armada 3720 Functional Specification Data Strobe applies for both read and write config requests. Data strobe bits configure which bytes from the start address should be returned for read request. Set value 0xf (all 4 bits) into Data Strobe register to read all four bytes from specified 32-bit config space register. Same value for Data Strobe register is programmed by Linux pci-aardvark.c driver for config read requests. Without this patch pci-aardvark driver sets data strobe register only during config write operations. So any followup config read operations could result with just partial datai returned (if previous write operation was not 32-bit wide). This patch fixes it and ensures that config read operations always read all bytes from requested register. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
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This is a pci driver, not an eth driver. Signed-off-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
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Root Complex should be the default mode, let's set it explicitly. Signed-off-by:
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Now that PCI Bridge is working, U-Boot's CONFIG_PCI_PNP code automatically enables memory access and bus mastering when it is needed. So do not prematurely enable memory access and bus mastering. Signed-off-by:
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PCI Bridge is always accessible also when link is down. So move detection of link up from mvebu_pcie_of_to_plat() function to mvebu_pcie_valid_addr() function which is used when accessing PCI config space. Signed-off-by:
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Functions mvebu_pcie_get_local_bus_nr() and mvebu_pcie_get_local_dev_nr() are not used, so remove them. Signed-off-by:
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The mysterious "Memory controller" PCI device which is present in PCI config space is improperly configured and crippled PCI Bridge which acts as PCIe Root Port for endpoint PCIe card. This PCI Bridge reports in PCI config space incorrect Class Code (Memory Controller) and incorrect Header Type (Type 0). It looks like HW bug in mvebu PCIe controller but apparently it can be changed via mvebu registers to correct values. The worst thing is that this PCI Bridge is crippled and its PCI config registers in range 0x10-0x34 alias access to internal mvebu registers which have different functionality as PCI Bridge registers. Moreover, configuration of PCI primary and secondary bus numbers (registers 0x18 and 0x19) is done via totally different mvebu registers via totally strange method and cannot be done via PCI Bridge config space. Due to above fact about PCI config range 0x10-0x34, allocate a private cfgcache[] buffer in the driver, to which PCI config access requests to the 0x10-0x34 space will be redirected in mvebu_pcie_read_config() and mvebu_pcie_write_config() functions. Function mvebu_pcie_write_config() will also catch writes to PCI_PRIMARY_BUS (0x18) and PCI_SECONDARY_BUS (0x19) registers and set PCI Bridge primary and secondary bus numbers via mvebu's own method. Also, Expansion ROM Base Address register (0x38) is available, but at different offset 0x30. So recalculate register offset before accessing PCI config space. After these steps U-Boot sees working PCI Bridge and CONFIG_PCI_PNP code can finally start enumerating all PCIe devices correctly, even with more complicated PCI topology. So update also mvebu_pcie_valid_addr() function to reflect state of the real device topology. Each PCIe port is de-facto isolated and every PCI Bridge which is part of PCIe Root Complex is also isolated, so put them on separate PCI buses as (local) device 0. U-Boot already supports enumerating separate PCI buses, real (HW) bus number can be retrieved by "PCI_BUS(bdf) - dev_seq(bus)" code, so update config read/write functions to properly handle more complicated tree topologies (e.g. when a PCIe switch with multiple PCI buses is connected to the PCIe port). Local bus number and local device number on mvebu are used for determining which config request type is used (Type 0 vs Type 1). On normal non-broken PCIe hardware it is done by primary and secondary bus numbers. So correctly translate settings between these numbers to ensure that correct config requests are sent over the PCIe bus. As bus numbers are correctly re-configured, it does not make sense to print some initial bogus configuration during probe, so remove this debug code. Signed-off-by:
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When reading 8 or 16 bits from config space, use appropriate readb() or readw() calls. This ensures that PCIe controller does not read more bits from endpoint card as asked by read_config() function. Technically there should not be an issue with reading data from config space which are not later used as there are no clear-by-read registers. But it is better to use correct read operation based on requested size. Signed-off-by:
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Current implementation of write_config() is broken for PCI_SIZE_8 or PCI_SIZE_16 as it always uses writel(), which means that write operation is always 32-bit, so upper 24 bits for PCI_SIZE_8 and upper 16 bits for PCI_SIZE_16 are cleared. Fix this by using writeb() and writew(), respectively. Signed-off-by:
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- Oct 31, 2021
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Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets introduced on March 2017. Features: - 8 Cortex A53 cores - ARM Mali-T830 MP3 GPU - LTE Cat. 7 (7880) or 6 (7870) modem Signed-off-by:Dzmitry Sankouski <dsankouski@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com>
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Iterate all pin banks to find a pin Signed-off-by: -
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Currently driver supports only version 1 and 2. Version 5 has slightly different registers structure Signed-off-by: -
Generic Interface (GENI) Serial Engine (SE) based uart can be found on newer qualcomm SOCs, starting from SDM845. Tested on Samsung SM-G9600(starqltechn) by chain-loading u-boot with stock bootloader. Signed-off-by: -
The DART is an IOMMU that is used on Apple's M1 SoC. This driver configures the DART such that it operates in bypass mode which is enough to support DMA for the USB3 ports integrated on the SoC. Signed-off-by:
Mark Kettenis <kettenis@openbsd.org> Reviewed-by:
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Apple M1 SoCs include an S5L UART which is a variant of the S5P UART. Add support for this variant and enable it by default on Apple SoCs. Signed-off-by:
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Add a set of tests for the IOMMU uclass. Signed-off-by:
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This uclass is intended to manage IOMMUs on systems where the IOMMUs are not in bypass mode by default. In that case U-Boot cannot ignore the IOMMUs if it wants to use devices that need to do DMA and sit behind such an IOMMU. This initial IOMMU uclass implementation does not implement and device ops and is intended for IOMMUs that have a bypass mode that does not require address translation. Support for IOMMUs that do require address translation is planned and device ops will be defined when support for such IOMMUs will be added. Signed-off-by:
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- Oct 30, 2021
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dev_err seems to be moved to different header file. Include dm/device_compat.h file to compile properly. Fixes: 69dae890 ("linux/compat.h: Remove redefinition of dev_xxx macros") Signed-off-by:
Stefan Agner <stefan@agner.ch>
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- Oct 29, 2021
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There are 4 registers (PERIPHID{0-3}) that contain the ID of MCI. For MMCs' with peripheral id 0x02041180 and 0x03041180, H/W flow control needs to be enabled for multi block writes (MMC CMD 18). Signed-off-by:Usama Arif <usama.arif@arm.com> Reviewed-by:
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Fix branching to avoid premature falling back on a long timeout instead of continuation of the initialization attempt. Clear of the comment to avoid the ambiguity. Signed-off-by:
Kirill Kapranov <kirill.kapranov@compulab.co.il> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Ye Li <ye.li@nxp.com> Reviewed-by:
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Adds an implementation of the wait_dat0 MMC operation for the DM SDHCI driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by:
Stephen Carlson <stcarlso@linux.microsoft.com> Signed-off-by:
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Adds an implementation of the wait_dat0 MMC operation for the Freescale eSHDC driver, allowing the driver to continue when the card is ready rather than waiting for the worst case time on each MMC switch operation. Signed-off-by:
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- Oct 26, 2021
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The DFU_MTD Kconfig entry is in the wrong position, move it into the correct alphabetically sorted position. No functional change. Signed-off-by:Marek Vasut <marex@denx.de> Cc: Lukasz Majewski <lukma@denx.de> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
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- Oct 25, 2021
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Not all SPI flashes and controllers can do continuous transfer longer than 16 MiB, so perform the DFU read in 16 MiB chunks. Signed-off-by:
Lukasz Majewski <lukma@denx.de>
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Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by:
Icenowy Zheng <icenowy@sipeed.com> Reviewed-by:
Andre Przywara <andre.przywara@arm.com> Signed-off-by:
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This driver supports the sun4i/sun6i/sun20i watchdog timers. They have a maximum timeout of 16 seconds. Signed-off-by:
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The sunxi clock driver exposes a reset controller, so it selects the reset controller framework. Ensure that dependency is also satisfied when building the driver for the SPL. Signed-off-by:
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The AXP PMICs have the ability to power off the system. The existing code for this is duplicated for each PMIC variant, and uses the legacy non-DM "pmic_bus" interface. When SYSRESET is enabled, this can all be replaced with a sysreset device using the DM_PMIC interface. Since the trigger bit is the same on all PMIC variants, use the register definitions from the oldest supported PMIC. Signed-off-by:
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